CY28312B-2
Table 3. Byte Read and Byte Write Protocol (continued)
Byte Write Protocol
Byte Read Protocol
Description
Acknowledge from slave
Bit
Description
Bit
29
30:37
38
Data byte from slave – 8 bits
Not Acknowledge
Stop
39
All unused register bits (reserved and N/A) should be written
to a “0” level.
CY28312B-2 Serial Configuration Map
The serial bits will be read by the clock driver in the following
order:
All register bits labeled “Initialize to 0” must be written to zero
during initialization.
Byte 0–Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1–Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte N–Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 0: Control Register 0
Bit
Pin#
Name
Default
Description
Bit 7
–
Spread Enable
0
0 = Disabled
1 = Enabled
Bit 6
Bit 5
Bit 4
–
–
–
Spread Select2
Spread Select1
Spread Select0
0
0
0
‘000’ = 0.25%
‘001’ = –0.5%
‘010’ = 0.5%
‘011’ = 0.38%
‘100’ = Reserved
‘101’ = Reserved
‘110’ = Reserved
‘111’ = Reserved
Bit 3
Bit 2
Bit 1
Bit 0
–
–
–
–
SEL3
SEL2
SEL1
SEL0
0
0
0
0
SW Frequency selection bits. See Table 4.
Byte 1: Control Register 1
Bit
Pin#
Name
Default
Description
(Active/Inactive)
Bit 7
Bit 6
42, 41
39, 38
CPUT0, CPUC0
1
1
CPUT_CS,
CPUC_CS
(Active/Inactive)
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
6
7
48MHz
24_48MHz
Reserved
AGP2
1
1
0
1
1
1
(Active/Inactive)
(Active/Inactive)
Reserved
–
28
27
26
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
AGP1
AGP0
Byte 2: Control Register 2
Bit Pin#
Name
PCI7
Default
Description
(Active/Inactive)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
20
18
17
16
14
1
1
1
1
1
PCI6
(Active/Inactive)
PCI5
(Active/Inactive)
PCI4
(Active/Inactive)
PCI3
(Active/Inactive)
Rev 1.0,November 21, 2006
Page 5 of 17
SPECTRALINEAR [ SPECTRALINEAR INC ]
