CY2277A
Function Table (-3)
CPUCLK[0:3]
SDRAM[0:7]
PCICLK[0:5]
PCICLK_F
REF[0:1]
IOAPIC
SEL
XTALIN
14.318 MHz
14.318 MHz
USBCLK / IOCLK[3]
0
1
33.33 MHz
66.67 MHz
16.67 MHz
33.33 MHz
14.318 MHz
14.318 MHz
48.0 MHz / 24.0 MHz
48.0 MHz / 24.0 MHz
Function Table (-1, -1M, -7M, -12, -12M, -12I)
CPUCLK[0:3]
SDRAM[0:7]
PCICLK[0:5]
PCICLK_F
REF[0:1]
IOAPIC
SEL
XTALIN
14.318 MHz
14.318 MHz
USBCLK / IOCLK[3]
48.0 MHz / 24.0 MHz
48.0 MHz / 24.0 MHz
0
1
60.0 MHz
66.67 MHz
30.0 MHz
33.33 MHz
14.318 MHz
14.318 MHz
Actual Clock Frequency Values (-1, -1M, -3, -7M, -12, -12M, -12I)
Target
Frequency (MHz)
Actual
Frequency (MHz)
Clock Output
CPUCLK, SDRAM
CPUCLK, SDRAM
USBCLK[4]
PPM
66.67
66.654
–195
0
60.0
48.0
24.0
60.0
48.008
24.004
167
167
IOCLK
• Output impedance: 25:ꢀ(typical) measured at 1.5V
CPU and PCI Clock Driver Strengths
• Matched impedances on both rising and falling edges on
the output drivers
Power Management Logic
CPU_STOP PCI_STOP PWR_DWN
CPUCLK
LOW
PCICLK
LOW
LOW
PCICLK_F Other Clocks
Osc.
Off
PLLs
Off
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
Stopped
Running
Stopped
Running
Running
Running
Running
LOW
LOW
Running Running
Running Running
Running Running
Running Running
33/30 MHz Running
Running
66/60 MHz LOW
66/60 MHz 33/30 MHz Running
Select Functions
Outputs
Functional Description
Three-State
CPU
PCI, PCI_F
Hi-Z
TCLK/4
SDRAM
Hi-Z
TCLK/2
Ref
Hi-Z
TCLK
IOAPIC
Hi-Z
IOCLK
USBCLK
Hi-Z
Hi-Z
TCLK/2[5]
Hi-Z
Test Mode
TCLK
TCLK/4
TCLK/2
Notes:
3. On power-up, the default frequency on these outputs is 48 MHz.
4. Meets Intel USB clock requirements.
5. TCLK supplied on the XTALIN, PIN 4.
Rev 1.0,November 25, 2006
Page 3 of 18
SPECTRALINEAR [ SPECTRALINEAR INC ]
