CY2210
Switching Characteristics[4, 5] Over the Operating Range
Parameter
t1
Output
Description
Output Duty Cycle[6]
Rising Edge Rate
Test Conditions
Min.
45
Max.
55
Unit
%
All
t1A/t1B
t2
CPU, CPU/2,
APIC
Between 0.4V and 2.0V
1.0
4.0
V/ns
t2
t2
t3
USB, REF
PCI, AGP
Rising Edge Rate
Rising Edge Rate
Falling Edge Rate
Between 0.4V and 2.4V
Between 0.4V and 2.4V
Between 2.0V and 0.4V
0.5
1.0
1.0
2.0
4.0
4.0
V/ns
V/ns
V/ns
CPU, CPU/2,
APIC
t3
USB, REF
PCI, AGP
CPU
Falling Edge Rate
Falling Edge Rate
CPU-CPU Skew
CPU/2-CPU/2 Skew
APIC-APIC Skew
AGP-AGP Skew
PCI-PCI Skew
Between 2.4V and 0.4V
Between 2.4V and 0.4V
Measured at 1.25V
Measured at 1.25V
Measured at 1.25V
Measured at 1.5V
0.5
1.0
2.0
4.0
V/ns
V/ns
ps
t3
t6
175
175
250
250
500
1.5
t7
CPU/2
APIC
ps
t8
ps
t9
AGP
ps
t10
t11
PCI
Measured at 1.5V
ps
CPU, AGP
CPU-AGP Clock Skew
CPU leads. Measured at 1.25V for
2.5V clocks and 1.5V for 3.3V clocks
0
ns
t12
t13
t14
AGP, PCI
CPU, APIC
CPU, PCI
AGP-PCI Clock Skew
CPU-APIC Clock Skew
CPU-PCI Clock Skew
AGP leads. Measured at 1.5V
CPU leads. Measured at 1.25V
1.5
1.5
1.5
4.0
4
ns
ns
ns
CPU leads. Measured at 1.25V clocks
and 1.5V for 3.3V clocks
4
CPU
CPU
Cycle-Cycle Clock Jitter
Cycle-Cycle Clock Jitter
With all outputs running (CY2210-2)
150
250
ps
ps
With all outputs running
(CY2210-3/-4)
CPU
Cycle-Cycle Clock Jitter
With the USB output turned off
(CY2210-3/-4)
200
ps
CPU/2
APIC
Cycle-Cycle Clock Jitter
Cycle-Cycle Clock Jitter
Cycle-Cycle Clock Jitter
Cycle-Cycle Clock Jitter
Cycle-Cycle Clock Jitter
Settle Time
250
500
500
500
1000
3
ps
ps
ps
ps
ps
ms
USB
AGP
REF
CPU, PCI
CPU and PCI clock stabilization from
power-up
Notes:
5. All parameters specified with loaded outputs.
6. Duty cycle is measured at 1.5V when V = 3.3V. When V = 2.5V, duty cycle is measured at 1.25V.
DD
DD
Rev 1.0,November 25, 2006
Page 5 of 10
SPECTRALINEAR [ SPECTRALINEAR INC ]
