SL74HC323
FUNCTION TABLE
Inputs
Output
Enables
Response
Mode Reset Mode
Select
Clock
Serial PA/ PB/ PC/ PD/ PE/ PF/ PG/ PH/ QA’ QH’
Inputs QA QB QC QD QE QF QG QH
S2 S1 OE1 OE2
DA DH
Reset
L
L
L
H
X
L
H
L
L
X
H
H
L
L
L
L
X
X
X
D
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
D
L
L
X
H
X
X
X
QA through QH=Z
L
Shift
Right
Shift Right: QA through QH=Z;
DA FA; FA FB; etc
QG
H
H
H
H
H
H
L
L
H
H
L
L
L
H
X
L
H
L
D
D
X
X
X
X
X
X
D
D
D
X
Shift Right: QA through QH=Z;
DA FA; FA FB; etc
D
D
QG
QG
D
Shift Right: DA FA =QA;
FA
Shift Left: QA through QH=Z;
DH FH; FH FG; etc
FB =QB; etc
Shift
Left
H
H
H
H
H
X
L
X
H
L
QB
QB
QB
PA
Shift Left: QA through QH=Z;
DH FH; FH FG; etc
D
Shift Left: DH
FH =QH;
D
FH
FG =QG; etc
Parallel
Load
X
X
Parallel Load:PN
FN
PH
Hold
H
H
H
L
L
L
L
L
L
H
X
L
X
H
L
X
X
X
X
X
X
X
X
X
Hold: QA through QH=Z; FN=FN
Hold: QA through QH=Z; FN=FN
Hold: QN =QH
PA
PA
PA
PH
PH
PH
Z = high impedance
D = data on serial input
F = flip-flop (see Logic Diagram)
When one or both output controls are high the eight input/output terminals are disabled to the high-impedance
state; however, sequential operation or clearing of the register is not affected.
System Logic
SLS
SLS [ SYSTEM LOGIC SEMICONDUCTOR ]
