SL74HC323
TIMING REQUIREMENTS(CL=50pF,Input tr=tf=6.0 ns)
VCC
Guaranteed Limit
Symbol
tsu
Parameter
V
25 °C to-55°C
£85°C
£125°C
Unit
ns
Minimum Setup Time, Mode Select S1
or S2 to Clock (Figure 4)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
tsu
Minimum Setup Time, Data Inputs SA,
SH, PA thru PH to Clock
(Figure 4)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
ns
ns
ns
ns
ns
th
Minimum Hold Time, Clock to Mode
Select S1 or S2 (Figure 4)
2.0
4.5
6.0
120
24
20
150
30
26
180
36
31
th
Minimum Hold Time, Clock to Data
Inputs, SA, SH, PA thru PH (Figure 4)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
tw
Minimum Pulse Width, Clock (Figure
1)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
tw
Minimum Pulse Width, Reset (Figure
2)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
tr, tf
Maximum Input Rise and Fall Times
(Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
System Logic
SLS
SLS [ SYSTEM LOGIC SEMICONDUCTOR ]
