Preliminary
STK14EC8
1
2
3
4
5
6
HSB
NC
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
A0
2
NC
G
A0
A3
A5
A1
A4
A6
A2
E
NC
NC
A
B
C
D
E
F
3
A1
A18
A17
A16
4
NC NC
DQ0 NC
A2
A3
5
6
NC DQ4
A4
E
A15
7
8
G
VSS DQ1 A17
VCC DQ2 VCAP A16 DQ6 VSS
DQ3 NC
NC HSB A12 A13
A18 A8
A7 DQ5 VCC
DQ0
DQ7
DQ6
VSS
VCC
9
DQ1
VCC
VSS
10
11
12
13
14
15
16
17
18
19
20
21
22
(TOP)
A14 A15 NC DQ7
NC
A10 A11 NC
(TOP)
48-Ball FBGA
DQ2
DQ3
DQ5
DQ4
W
G
H
VCAP
A14
W
A5
A6
A7
A9
A13
A12
A11
A10
A8
A9
NC
NC
NC
NC
(See mechanical drawing on page 18)
44-Pin TSOP-II
(See mechanical drawing on page 17)
PIN DESCRIPTIONS
Pin Name
-A
I/O
Description
A
Input
I/O
Address: The 19 address inputs select one of 524,288 bytes in the nvSRAM array
18
0
DQ -DQ
7
Data: Bi-directional 8-bit data bus for accessing the nvSRAM
Chip Enable: The active low E input selects the device
0
E
Input
Input
W
Write Enable Input, Active Low: When selected low, enables data on the IO pins to be written to the address
location latched by the falling edge of CE.
G
Input
Output Enable: The active low G input enables the data output buffers during read cycles. De-asserting G high
causes the DQ pins to tri-state.
V
Power Supply
I/O
Power: 3.0V, +20%, -10%
CC
HSB
Hardware Store Busy: When low this output indicates a Store is in progress (also low during power up while
busy). When pulled low external to the chip, it will initiate a nonvolatile STORE operation. A weak pull up resis-
tor keeps this pin high if not connected. (Connection Optional).
V
V
Power Supply
Autostore Capacitor: Supplies power to the nvSRAM during a power loss to store data from SRAM to nonvol-
atile storage elements.
CAP
Power Supply
No Connect
Ground
SS
NC
This pin is not connected to the die. (Do not connect in design; reserved for future use)
Rev 1.1
Document Control #ML0060
Jan, 2008
2
Simtek Confidential
SIMTEK [ SIMTEK CORPORATION ]
