STK10C68-M
(VCC = 5.0V ± 10%)
WRITE CYCLES #1 & #2; G high
SYMBOLS
NO.
STK10C68-35M
STK10C68-45M
STK10C68-55M
UNITS
PARAMETER
#1
#2
Alt.
MIN
MAX
MIN
MAX
MIN
MAX
12
13
14
15
16
17
18
19
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
Write Pulse Width
35
30
30
18
0
45
35
35
20
0
55
45
45
30
0
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
AVAV
WLEH
ELEH
DVEH
EHDX
AVEH
AVEL
EHAX
WC
t
WLWH
ELWH
DVWH
WHDX
AVWH
AVWL
WHAX
WP
t
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold After End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold After End of Write
CW
t
DW
t
DH
t
30
0
35
0
45
0
AW
t
AS
t
0
0
0
WR
(VCC = 5.0V ± 10%)
WRITE CYCLES #1 & #2; G low
SYMBOLS
NO.
STK10C68-35M
STK10C68-45M
STK10C68-55M
UNITS
PARAMETER
#1
#2
Alt.
MIN
MAX
MIN
MAX
MIN
MAX
12
13
14
15
16
17
18
19
20
21
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
Write Pulse Width
45
35
35
30
0
45
35
35
30
0
55
45
45
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
AVAV
WLEH
ELEH
DVEH
EHDX
AVEH
AVEL
EHAX
WC
t
WLWH
ELWH
DVWH
WHDX
AVWH
AVWL
WHAX
WP
t
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold After End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold After End of Write
Write Enable to Output Disable
Output Active After End of Write
CW
t
DW
t
DH
t
35
0
35
0
45
0
AW
t
AS
t
0
0
0
WR
i,m
t
35
35
35
WLQZ
WZ
t
5
5
5
WHQX
OW
Note f: NE must be ≥ V during entire cycle.
IH
Note i: Measured + 200mV from steady state output voltage.
Note k: E or W must be ≥ V during address transitions.
IH
Note m: If W is low when E goes low, the outputs remain in the high impedance state.
4-14
SIMTEK [ SIMTEK CORPORATION ]
