Si500D
Parameters
Output Symmetry
Condition
= 0
Min
Typ
—
Max
54 + 13 ns/T
460
Units
%
V
46 – 13 ns/T
DIFF
CLK
CLK
LVPECL/LVDS
HCSL/Differential SSTL
Differential CMOS, 15 pF, >80 MHz
Mid-level
—
—
—
—
ps
3
Rise and Fall Times (20/80%)
—
800
ps
1.1
—
1.6
ns
V
– 1.5
V
– 1.34
V
LVPECL Output Option
DD
DD
3
(DC coupling, 50 to V – 2.0 V)
Diff swing
.720
—
.880
V
DD
PK
Low Power LVPECL Output Option
Mid-level
—
N/A
—
V
(AC coupling, 100 Differential
Load)
Diff swing
.68
—
.95
V
3
PK
Mid-level
Diff swing
1.15
0.25
0.85
0.25
0.35
0.65
45
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1.26
0.45
0.96
0.45
0.425
0.82
55
V
LVDS Output Option (2.5/3.3 V)
3
(R
= 100 diff)
V
TERM
PK
Mid-level
V
LVDS Output Option (1.8 V)
3
(R
= 100 diff)
Diff swing
V
TERM
PK
Mid-level
V
3
HCSL Output Option
Diff swing
V
PK
DC termination per pad
V
V
V
, sourcing 9 mA
V
– 0.6
DD
—
OH
3
CMOS Output Voltage
V
, sinking 9 mA
—
0.6
OL
V
V
+ 0.375
—
—
OH
TT
4
4
5
SSTL-1.8 Output Voltage
SSTL-2.5 Output Voltage
SSTL-3.3 Output Voltage
Powerup Time
V
V
V
V
V
– 0.375
—
OL
TT
V
V
+ 0.48
—
OH
TT
V
V
V
– 0.48
—
OL
TT
TT
V
V
+ 0.48
—
OH
TT
V
– 0.48
OL
From time V crosses min spec
DD
—
—
—
—
—
—
2
ms
ns
ns
supply
OE Deassertion to Clk Stop
250 + 3 x T
250 + 3 x T
CLK
CLK
CLK
Return from Output Driver Stopped
Mode
Return From Tri-State Time
—
—
—
—
12 + 3 x T
2
µs
Return From Powerdown Time
ms
ps
RMS
Non-CMOS
—
—
—
—
1
2
3
Period Jitter (1-sigma)
ps
RMS
CMOS, C = 7 pF
1
L
1.0 MHz – min(20 MHz,
ps
RMS
0.6
0.7
1
0.4 x F
),non-CMOS
OUT
Integrated Phase Jitter
1.0 MHz – min(20 MHz,
0.4 x F ),CMOS format
ps
RMS
1.5
OUT
Notes:
1. Inclusive of 25 °C initial frequency accuracy, operating temperature range, supply voltage change, output load change,
first-year aging at 25 °C, shock, vibration, and one solder reflow.
2. Inclusive of 25 °C initial frequency accuracy, operating temperature range, supply voltage change, output load change,
ten-year aging at 85 °C, shock, vibration, and one solder reflow.
3. See “AN409: Output Termination Options for the Si500S and Si500D Silicon Oscillators” for further details regarding
output clock termination recommendations.
4. VTT = .5 x VDD
.
5. VTT = .45 x VDD
.
2
Rev. 1.0
SILICON [ SILICON ]
