E0C88862
■ BASIC EXTERNAL CONNECTION DIAGRAM
● When piezoelectric buzzer is driven with single terminal and LCD panel is driven with 1/5 bias power supply
LCD panel 41 x 32
VSS
N.C.
V
OSC
2
4
1
3
C
G1
OSC1
K00
K01
K02
K03
K04
K05
K06
K07
K10
X'tal1
OSC2
OSC3
CG2
X'tal2 or
Ceramic
Rf
OSC4
CD2
C
1
2
3
4
5
6
VD1
VC1
VC2
VC3
VC4
VC5
C
C
C
C
C
E0C88862
[The potential of the substrate
R26 (TOUT)
R27 (TOUT)
R51 (BZ)
CA
(back of the chip) is VSS.]
C
7
8
CB
C
CC
P10 (SIN)
P11 (SOUT)
P12 (SCLK)
P13 (SRDY)
P14
CD
C9
CE
CF
C10
CG
RESET
P15
P16
Cres
P17
-
+
C
P
3 V
VDD
TEST
Piezo
Coil
Recommended values for external parts
Symbol
Name
Recommended value
32.768 kHz, CI (Max.)=35 kΩ
5–25 pF
Symbol
Name
Recommended value
X'tal1 Crystal oscillator
R
C
C
C
C
C
C
C
C
CR3
Resistor for CR oscillation
20 kΩ
CG1
Trimmer capacitor
1
2
3
4
5
6
Capacitor between VSS and VD1 0.1 µF
Capacitor between VSS and VC1 0.1 µF
Capacitor between VSS and VC2 0.1 µF
Capacitor between VSS and VC3 0.1 µF
Capacitor between VSS and VC4 0.1 µF
Capacitor between VSS and VC5 0.1 µF
RCR1
Resistor for CR oscillation 800 kΩ
X'tal2 Crystal oscillator
Ceramic Ceramic oscillator
4.9152 MHz
4 MHz
Rf
Feedback resistor
Gate capacitor
1 MΩ
CG2
15 pF (Crystal osciilation)
30 pF (Ceramic osciilation)
15 pF (Crystal osciilation)
30 pF (Ceramic osciilation)
7–C10 Booster/reducer capacitors
0.1 µF
3.3 µF
0.47 µF
CD2
Drain capacitor
P
Capacitor for power supply
Cres
Capacitor for RESET terminal
The connection diagram shown above is an example of when mask option settings are as follows:
LCD power source: Internal power supply (1/5 bias), RESET terminal: With pull-up resistor,
R51 specification: General-purpose output port
1 OSC1 = Crystal oscillation, 2 OSC1 = CR oscillation, 3 OSC3 = Crystal/Ceramic oscillation, 4 OSC3 = CR oscillation
Note: The above table is simply an example, and is not guaranteed to work.
9
SEIKO [ SEIKO EPSON CORPORATION ]
