E0C88112
Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name
1
2
3
4
5
6
7
8
9
N.C.
N.C.
N.C.
RESET
N.C.
K11/BREQ 31 R03/A3
K10/EVIN
K07
26 N.C.
27 N.C.
28 R00/A0
29 R01/A1
30 R02/A2
51 N.C.
52 N.C.
53 R24/WR
54 R25
55 R26
76 N.C.
77 N.C.
78 N.C.
79 R50/BZ
80 R51/BACK
QFP15-100pin
75
51
56 R27/TOUT 81 P17/CMPM1
76
50
32 R04/A4
33 R05/A5
34 R06/A6
35 R07/A7
36 R10/A8
37 R11/A9
38 R12/A10
39 R13/A11
40 R14/A12
57 R30/CE0
58 R31/CE1
59 R32/CE2
60 R33/CE3
82 P16/CMPP1
83 P15/CMPM0
84 P14/CMPP0
85 P13/SRDY
K06
10 K05
11 K04
12 K03
13 K02
14 K01
15 K00
16 MCU/MPU 41 R15/A13
17
18 OSC4
19 OSC3
20
21 OSC2
22 OSC1
23
24 N.C.
25 N.C.
61 R34/FOUT 86 P12/SCLK
62 R35
63 R36
64 R37
65
66
67
68
69
70
71
87 P11/SOUT
88 P10/SIN
89 P07/D7
90 P06/D6
91 P05/D5
92 P04/D4
93 P03/D3
94 P02/D2
95 P01/D1
96 P00/D0
97 N.C.
E0C88112
INDEX
VDD
42 R16/A14
43 R17/A15
44 R20/A16
45 R21/A17
46 R22/A18
47 R23/RD
48 N.C.
100
26
VD1
1
25
72
VSS
73 N.C.
74 N.C.
75 N.C.
98 TEST
99 N.C.
100 N.C.
49 N.C.
50 N.C.
Pins No. 65 to 72 are the pads used for outgoing inspection of the IC. Do not connect anything to these pins.
N.C. : No Connection
■ PIN DESCRIPTION
Pin No.
QFP14-80 QFP15-100
Pin name
In/Out
Function
VDD
VSS
VD1
OSC1
OSC2
74
80
77
79
78
76
75
73
72–65
64
17
23
20
22
21
19
18
16
15–8
7
–
–
–
I
O
I
O
I
I
Power supply (+) terminal
Power supply (GND) terminal
Regulated voltage output terminal for oscillators
OSC1 oscillation input terminal (crystal oscillation/CR oscillation/external clock input, mask option)
OSC1 oscillation output terminal
OSC3 oscillation input terminal (crystal/ceramic/CR oscillation/external clock input, mask option)
OSC3 oscillation output terminal
Terminal for setting MCU or MPU modes
OSC3
OSC4
MCU/MPU
K00–K07
K10/EVIN
K11/BREQ
R00–R07/A0–A7
R10–R17/A8–A15
R20–R22/A16–A18
R23/RD
R24/WR
R25
R26
R27/TOUT
Input port (K00–K07) terminal
I
I
Input port (K10) terminal or event counter external clock (EVIN) input terminal
Input port (K11) terminal or bus request signal (BREQ) input terminal
Output port (R00–R07) terminals or address bus (A0–A7)
Output port (R10–R17) terminals or address bus (A8–A15)
Output port (R20–R22) terminals or address bus (A16–A18)
Output port (R23) terminal or read signal (RD) output terminal
Output port (R24) terminal or write signal (WR) output terminal
Output port (R25) terminal
63
6
1–8
9–16
17–19
20
21
22
28–35
36–43
44–46
47
53
54
O
O
O
O
O
O
O
O
23
24
55
56
Output port (R26) terminal
Output port (R27) terminal
or programmable timer underflow signal (TOUT) output terminal
Output port (R30–R33) terminals or chip enable (CE0–CE3) output terminals
Output port (R34) terminal or clock (FOUT) output terminal
Output port (R35–R37) terminal
Output port (R50) terminal or buzzer (BZ) output terminal
Output port (R51) terminal or bus acknowledge signal (BACK) output terminal
R30–R33/CE0–CE3 25–28
57–60
61
62–64
79
80
96–89
88
87
86
85
84
O
O
O
O
O
R34/FOUT
R35–R37
R50/BZ
29
30–32
41
R51/BACK
P00–P07/D0–D7
P10/SIN
42
58–51
50
I/O I/O port (P00–P07) terminals or data bus (D0–D7)
I/O I/O port (P10) terminal or serial I/F data input (SIN) terminal
I/O I/O port (P11) terminal or serial I/F data output (SOUT) terminal
I/O I/O port (P12) terminal or serial I/F clock (SCLK) I/O terminal
I/O I/O port (P13) terminal or serial I/F ready signal (SRDY) output terminal
I/O I/O port (P14) terminal or comparator 0 non-inverted input terminal
I/O I/O port (P15) terminal or comparator 0 inverted input terminal
I/O I/O port (P16) terminal or comparator 1 non-inverted input terminal
I/O I/O port (P17) terminal or comparator 1 inverted input terminal
P11/SOUT
P12/SCLK
P13/SRDY
P14/CMPP0
P15/CMPM0
P16/CMPP1
P17/CMPM1
RESET
49
48
47
46
45
44
43
61
83
82
81
4
I
I
Initial reset input terminal
Test input terminal
TEST
60
98
TEST is the terminal used for outgoing inspection of the IC. For normal operation be sure it is connected to VDD.
3
SEIKO [ SEIKO EPSON CORPORATION ]
