E0C6S37
■ BLOCK DIAGRAM
OSC1 OSC2
OSC
RESET
ROM
System Reset
Control
1,024 words x 12 bits
Core CPU E0C6200A
RAM
80 words x 4 bits
Interrupt
Generator
COM0
–COM3
SEG0
K00–K03
TEST
Input Port
Test Port
LCD Driver
–SEG25
P00–P03
R00–R03
I/O Port
Output Port
V
DD
V
L1–VL3
CA, CB
Power
Controller
V
V
S1
SS
SVD
Clock Timer
Stopwatch Timer
FOUT
&
BUZZER
■ PIN CONFIGURATION
Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name
QFP6-60pin
1
2
3
4
5
6
7
8
9
OSC1
OSC2
N.C.
16 COM2
17 COM3
18 SEG0
19 SEG1
20 SEG2
21 SEG3
22 SEG4
23 SEG5
24 SEG6
25 SEG7
26 SEG8
27 SEG9
28 SEG10
29 SEG11
30 SEG12
31 TEST
46 P01
47 P02
48 P03
49 RESET
50 K00
51 K01
52 K02
53 K03
54 R00
55 R01
56 R02
57 R03
58 N.C.
45
31
32 SEG13
33 SEG14
34 SEG15
35 SEG16
36 SEG17
37 SEG18
38 SEG19
39 SEG20
40 SEG21
41 SEG22
42 SEG23
43 SEG24
44 SEG25
45 P00
V
S1
46
30
N.C.
CA
CB
N.C.
N.C.
E0C6S37
INDEX
10 N.C.
11
12
13
V
V
V
L1
L2
L3
60
16
14 COM0
15 COM1
59
60
V
V
SS
1
15
DD
N.C. : No Connection
2