E0C63256
• K03 external clock (event counter external clock)
(Unless otherwise specified: VDD=2.7 to 5.5V, VSS=0V, Ta=-20 to 85°C, VIH1=0.8·VDD, VIL1=0.2·VDD
)
Characteristic
Input clock cycle time
Input clock "H" pulse width
Input clock "L" pulse width
Input clock cycle time
Input clock "H" pulse width
Input clock "L" pulse width
Input clock rising time
Symbol
Condition
Min.
512·n/fOSC
256·n/fOSC
256·n/fOSC
Max.
Unit Note
t
t
t
t
t
t
t
t
evcy With noise rejecter
evh
evl
S
S
S
1
1
1
evcy Without noise rejecter
4
2
2
µS
µS
µS
nS
nS
evh
evl
osr
osf
25
25
Input clock falling time
Note) 1. fOSC: oscillation clock frequency, n=1–16: PRSM setting value + 1
tevcy
tevh
t
V
evf
IH1
IL1
K03
V
tevr
tevl
• RESET input clock
(Unless otherwise specified: VDD=2.7 to 5.5V, VSS=0V, Ta=-20 to 85°C, VIH=0.5·VDD, VIL=0.1·VDD
)
Unit Note
µS
Characteristic
RESET input time
Symbol
sr
Condition
Min.
100
Max.
t
t
sr
V
IH
RESET
V
IL
• K00–K03 simultaneous low input clock
(Unless otherwise specified: VDD=2.7 to 5.5V, VSS=0V, Ta=-20 to 85°C, VIH1=0.8·VDD, VIL1=0.2·VDD
)
Characteristic
Symbol
Condition
Min.
Max.
Unit Note
Simultaneous low input time
t
ksr Time authorize circuit is used
Time authorize circuit is not used
524288·n/fOSC
768·n/fOSC
S
S
1
1
Note) 1. fOSC: oscillation clock frequency, n=1–16: PRSM setting value + 1
When the simultaneous low input reset function is selected by mask option.
t
ksr
VIH1
K0x
VIL1
Power-on Reset
(Unless otherwise specified: VSS=0V, Ta=-20 to 85°C, VIH=0.5·VDD, VIL=0.1·VDD
)
Characteristic
Operating power voltage
RESET input time
Symbol
Vsr RESET=0.1·VDD
psr
Condition
Min.
2.7
100
Typ.
Max.
Unit Note
V
µS
t
V
DD
Vsr
2
1
V
DD
t
psr
RESET
0.5·VDD
0.1·VDD
RESET
V
SS
Power on
1 Because the potential of the RESET terminal
not reached VDD level or higher.
2 When the built-in pull-up resistor is not used.
A/D Conversion Characteristics
(Unless otherwise specified: VDD=2.7 to 5.5V, VSS=AVSS=0V, Ta=-20 to 85°C)
Characteristic
A/D conversion time
Sampling time
Symbol
Condition
AD=240kHz to 2.5MHz
AD=240kHz to 2.5MHz
Min.
20
Typ.
Max.
21
Unit Note
t
t
ADC
f
f
clock
clock
1
1
SMP
8
Note) 1. fAD=fPRS=fOSC/2n or fAD=fOSC/2 (fAD: A/D conversion clock frequency, fOSC: oscillation clock frequency, n=1–16: PRSM setting value + 1)
8
SEIKO [ SEIKO EPSON CORPORATION ]
