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E0C63256F 参数 Datasheet PDF下载

E0C63256F图片预览
型号: E0C63256F
PDF下载: 下载PDF文件 查看货源
内容描述: [4-BIT, MROM, 4.5MHz, MICROCONTROLLER, PQFP64, QFP13-64]
分类和应用: 时钟外围集成电路
文件页数/大小: 12 页 / 113 K
品牌: SEIKO [ SEIKO EPSON CORPORATION ]
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E0C63256  
Analog Circuit Characteristics  
LCD Drive Voltage Characteristics  
(Unless otherwise specified: VDD=2.7 to 5.5V, VSS=0V, VC2/VC1 are internal voltage, Ta=-20 to 85°C, C  
2=C3=0.1µF)  
Characteristic  
LCD supply voltage  
LCD drive voltage  
Symbol  
Condition  
Min.  
2.7  
Typ.  
Max.  
5.5  
Unit Note  
V
C3I  
VC3  
V
V
1
2
VC1  
Connect 1 Mload resistor between VSS or VDD Typ. - 0.2  
and VC1 (without panel load)  
Connect 1 Mload resistor between VSS or VDD Typ. - 0.2  
and VC2 (=VC2) (without panel load)  
V
V
V
C3·1/3 Typ. + 0.2  
C3·2/3 Typ. + 0.2  
C3·1/2 Typ. + 0.2  
(when 1/3 bias is selected)  
V
V
R
C2  
V
V
2
2
2
LCD drive voltage  
(when 1/2 bias is selected)  
Built-in resistance  
C1&2 Connect 1 Mload resistor between VSS or VDD and  
C1(=VC2)(without panel load), VC1 and VC2 are shorted  
LCD Resistance between VC3 and VSS  
Typ. - 0.2  
V
30  
50  
100  
kΩ  
Note) 1. When "Internal power (external VC3 is used)" is selected by mask option.  
2. VC3 = VDD when "Internal power (external VC3 is not used)" is selected by mask option.  
A/D Conversion Characteristics  
(Unless otherwise specified: VDD=2.7 to 5.5V, VSS=AVSS=0V, Ta=-20 to 85°C)  
Characteristic  
Analog supply voltage  
Analog reference voltage range  
Analog input voltage range  
Analog input capacitance  
Analog reference resistance  
Resolution  
Symbol  
Condition  
AVDD  
AVREF  
Min.  
2.7  
2.7  
Typ.  
Max.  
Unit Note  
V
V
VAVDD  
VREF  
VIN  
VDD  
AVDD  
AVREF  
60  
30  
8
AD0 to AD3 (P40 to P43)  
AD0 to AD3 (P40 to P43)  
REF Resistance for AVREF–AVSS  
AVSS  
V
C
R
AIN  
During sampling  
35  
20  
pF  
kΩ  
bit  
10  
Offset error  
Full scale error  
Non-linearity error  
Overall error  
A/D conversion time  
Sampling time  
E
E
E
E
OFF  
AVDD=2.7V to VDD  
AVREF=2.7V to AVDD  
-1  
-1  
-2  
-2  
20  
1
1
4
4
LSB  
LSB  
LSB 1,2  
LSB 1,2  
clock  
clock  
1
1
FS  
LI  
T
f
AD=240kHz to 2.5MHz  
t
t
ADC  
SMP  
f
f
AD=240kHz to 2.5MHz  
AD=240kHz to 2.5MHz  
21  
1
1
8
Note) 1.  
fAD=fPRS=fOSC/2n or fAD=fOSC/2 (fAD: A/D conversion clock frequency, fOSC: oscillation clock frequency, n=1–16: PRSM setting value + 1)  
2. The best straight line within a ±3LSB of error can be obtained by correcting the conversion result with -1LSB by software.  
a
c
FFH  
Ideal line  
b
Real conversion curve  
End point line  
00H  
AVSS  
AVREF  
Analog input voltage VIN  
Offset error  
: EOFF = a (the deviation from the ideal value at zero point)  
Non-linearity error : ELI = b (the deviation of the real conversion curve from the end point line)  
Full scale error  
: EFS = c (the deviation from the ideal value at the full scale point)  
Total error  
: E  
E
T
= max (EOFF, ELI, EABS  
)
ABS = the deviation from the ideal line (including quantizing error)  
6