E0C63158
● Timing Chart
Reset
Supply voltage
3 sec
6 msec min.
(fOSC1 = 32.768 kHz)
OSC1 oscillation clock
Oscillation unstabilized state
RESET terminal
(active-Low)
Internal reset signal
(active-High)
System clock switching
1 instruction execution time or longer
VDC
2.5 msec min.
5 msec min.
OSCC
CLKCHG
(Note) When the OSC1 oscillation circuit has been selected as the CR oscillation circuit,
it is not necessary to set the VDC register.
Whether the VDC register value is "1" or "0" does not matter.
Supply voltage VC2 mode control during heavy load driving
1 instruction execution time or longer
DBON
100 msec min.
100 msec min.
1 msec min.
VDSEL
VADSEL (Note)
2 sec min.
ON
Heavy load
OFF
(Note) VADSEL is used only when it is required.
9
SEIKO [ SEIKO EPSON CORPORATION ]
