E0C624A
■ PIN DESCRIPTION
Pin name
Pin No.
In/Out
Function
V
V
V
V
V
DD
SS
S1
125
117
122
I
I
–
–
O
–
Power source (+) terminal
Power source (-) terminal
Oscillation and internal logic system regulated voltage
LCD system power (1/4 or 1/5 bias may be selected by mask option)
LCD system power test terminal
L1–VL5
REF
127, 128, 1–3
126
CA–CF
OSC1
10–6, 4
124
Booster capacitor connecting terminal
Crystal oscillation input terminal
I
OSC2
OSC3
OSC4
K00–K03, K10–K13
P00–P03, P10–P13
P20–P23
P30–P33
R00–R03, R10–R13
R20–R23, R30
R31
R32
R33
R40
R41
R42
R43
SIN
SOUT
123
121
120
79–72
95–88
87–84
83–80
116–104
O
I
O
I
I/O
I/O
I/O
O
Crystal oscillation output terminal
Ceramic or CR oscillation input terminal (selected by mask option)
Ceramic or CR oscillation output terminal (selected by mask option)
Input terminal (Use of pull up resistor is selected by mask option)
I/O terminal (Setting for data bus may be selected by mask option)
I/O terminal (CS output may be selected by mask option)
I/O terminal
Output terminal (Setting for address bus may be selected by mask option)
103
102
101
100
99
97
96
71
70
O
O
O
O
O
O
O
I
O
I/O
O
O
I
Output terminal (DC, address or WR output may be selected by mask option)
Output terminal (DC or RD output may be selected by mask option)
Output terminal (DC or SRDY output may be selected by mask option)
Output terminal (DC, CL or FOUT output may be selected by mask option)
Output terminal (DC or FR output may be selected by mask option)
Output terminal (DC, BZ or FOUT output may be selected by mask option)
Output terminal (DC or BZ output may be selected by mask option)
Serial interface input terminal
Serial interface output terminal
Serial interface clock input/output terminal
LCD segment output terminal
LCD common output terminal
SCLK
68
SEG0–39
COM0–15
RESET
TEST
67–35, 33–27
11–26
118
Initial reset input terminal
Test input terminal
119
I
■ BASIC EXTERNAL CONNECTION DIAGRAM
LCD PANEL 120 x 16
X'tal
Crystal oscillator
32.768kHz
CI(Max.)=35kΩ
Rfx
Feedback resistor 10MΩ
SEG0~SEG79
SEG0~SEG39
COM0~COM15
K00~K03
K10~K13
KEY
MATRIX
8 x 6
Cgx
Trimmer capacitor 5~25pF
P22~P23
P30~P33
Ceramic Ceramic oscillator 500kHz~2MHz
Rfc
Feedback resistor 1MΩ
Gate capacitance 100pF
Drein capacitance 100pF
SIN
SOUT
SCLK
SERIAL
DEVICE
SED1521FAA
Cgc
Cdc
Rcr
P00~P03
P10~P13
DB0~DB7
R33
Resistance for
CR oscillation
20kΩ~100kΩ
R40
R41
R42
R43
Vss
VDD V2 V3 V5 CL FR RES RD WR
CS
A0
P20
P21
E0C624A
C1~C3 Voltage booster
capacitor (1)~(3)
0.1µF
1
1
1
1
1
Buzzer
N.C.
VREF
C4
C5
C6
C7
C8
Capacitor between 0.1µF
DD and VL1
Capacitor between 0.1µF
DD and VL2
Capacitor between 0.1µF
DD and VL4
Capacitor between 0.1µF
DD and VL5
Capacitor between 0.1µF
DD and VS1
R00~R03
R10~R13
R20~R23
R30
R31
R32
Vss
V
RESET
–
+
TEST
V
V
DD
CF CE CD CC CB CA VL5
C3 C2 C1
VL4
VL3
VL2
VL1
VS1 OSC4
OSC3 OSC2 OSC1
Rfc
Rfx
V
Ceramic
Cdc
X'tal
C7 C6
C5 C4 C8
V
Cgc
Cgx
Vss
DD
CS2
OE
V
A0~A12 WE
D0~D7 CS1
V
Rcr
1 When the load on the liquid
crystal system is large, increase
the capacitance of the voltage
booster capacitors (C1–C3) and
the capacitors between VDD and
liquid crystal system power
(C4–C7).
SRM2064
Power
5V
Note: • Since SRM2064 is applied in the external SRAM in this example, the power
supply voltage of 5 V is used.
• The above table is simply an example, and is not guaranteed to work.
3
SEIKO [ SEIKO EPSON CORPORATION ]
