CF5072 series
PAD LAYOUT
(Unit: µm)
(1820,1000)
VDD2
8
7
6
VDD1
OUTN
XIN
XC 10
9
NC 11
XR 12
VC 13
5
OUT
Y
4
3
VSS2
OE
2
VSS1
1
(0,0)
TEST
X
Chip size: 1.82 × 1.00mm
Chip thickness: 300 30ꢀm
Pad size: 110 × 100ꢀm (TEST pin only = 90 × 90ꢀm)
Chip base: V potential
SS
PAD DESCRIPTION AND DIMENSIONS
Pad dimensions [µm]
Pad size [µm]
Pad No.
Name
I/O
Function
X
Y
X
Y
1
2
VSS1
TEST
OE
–
I
Oscillator ground
125
135
160
135
268
460
673
865
865
828
708
495
375
255
110
90
100
90
IC test pin (leave open circuit for normal operation)
Output enable, with pull-up resistor built-in
Ground
1283
1695
1695
1695
1695
1695
643
3
I
110
110
110
110
110
100
110
110
110
110
110
100
100
100
100
100
110
100
100
100
100
100
4
VSS2
OUT
OUTN
VDD1
VDD2
XIN
–
O
O
–
–
I
5
Differential PECL non-inverting output (true)
Differential PECL inverting output (complementary)
ECL buffer supply
6
7
8
Supply
9
Crystal unit connection
125
10
11
12
13
XC
I
Varicap anode connection
125
NC
–
I
No connection
125
1
XR
Varicap cathode connection and inductor connection
Control voltage pin
125
VC
I
125
1. The XR pin electrostatic withstand voltage is weaker than the other pins. The electrostatic withstand voltage of pins, excluding XR, is the same as that
for existing NPC devices.
NIPPON PRECISION CIRCUITS INC.—3
SEIKO [ SEIKO EPSON CORPORATION ]
