IDT71016, CMOS Static RAM
1 Meg (64K x 16-bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle No. 2(1)
tRC
ADDRESS
tAA
t
OH
OE
(3)
tOE
tOHZ
,
(3)
tOLZ
CS
(2)
tACS
(3)
(3)
t
CHZ
tCLZ
BHE, BLE
(2)
(3)
t
BE
(3)
tBHZ
t
BLZ
DATAOUT
DATAOUT VALID
3210 drw 07
NOTES:
1. WE is HIGH for Read Cycle.
2. Address must be valid prior to or coincident with the later of CS, BHE, or BLE transition LOW; otherwise tAA is the limiting parameter.
3. Transition is measured ±200mV from steady state.
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4)
tWC
ADDRESS
t
AW
CS
(2)
(5)
t
CW
tCHZ
tBW
BHE BLE
,
(5)
tWR
t
BHZ
t
WP
WE
t
AS
(5)
tWHZ
(5)
t
OW
(3)
DATAOUT
DATAIN
PREVIOUS DATA VALID
DATA VALID
tDH
,
t
DW
DATAIN VALID
3210 drw 08
NOTES:
1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.
2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and
data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the
minimum write pulse is as short as the specified tWP.
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. Transition is measured ±200mV from steady state.
6.462
ROCHESTER [ Rochester Electronics ]
