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71016S15YG 参数 Datasheet PDF下载

71016S15YG图片预览
型号: 71016S15YG
PDF下载: 下载PDF文件 查看货源
内容描述: [64KX16 STANDARD SRAM, 15ns, PDSO44, 0.400 INCH, GREEN, PLASTIC, SOJ-44]
分类和应用: 静态存储器光电二极管内存集成电路
文件页数/大小: 10 页 / 2191 K
品牌: ROCHESTER [ Rochester Electronics ]
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IDT71016, CMOS Static RAM  
1 Meg (64K x 16-bit)  
Commercial and Industrial Temperature Ranges  
AC Electrical Characteristics (VCC = 5.0V ± 10%, Commercial and Industrial Range)  
71016S12  
71016S15  
71016S20  
Symbol  
Parameter  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Unit  
READ CYCLE  
____  
____  
____  
t
RC  
AA  
ACS  
Read Cycle Time  
12  
15  
20  
ns  
ns  
ns  
ns  
___ _  
____  
____  
t
Address Access Time  
Chip Select Access Time  
12  
15  
20  
___ _  
____  
____  
t
12  
15  
20  
____  
____  
____  
(1)  
Chip Select Low to Output in Low-Z  
Chip Select High to Output in High-Z  
Output Enable Low to Output Valid  
Output Enable Low to Output in Low-Z  
4
5
5
tCLZ  
___ _  
____  
____  
(1)  
6
6
8
ns  
ns  
ns  
tCHZ  
___ _  
____  
____  
tOE  
7
8
10  
____  
____  
____  
(1)  
0
0
0
tOLZ  
___ _  
____  
____  
(1)  
OHZ  
Output Enable High to Output in High-Z  
Output Hold from Address Change  
Byte Enable Low to Output Valid  
Byte Enable Low to Output in Low-Z  
6
6
8
ns  
ns  
ns  
ns  
t
____  
____  
____  
tOH  
4
4
5
___ _  
____  
____  
tBE  
7
8
10  
(1)  
BLZ  
____  
____  
____  
0
0
0
t
___ _  
____  
____  
(1)  
BHZ  
Byte Enable High to Output in High-Z  
6
6
8
ns  
t
WRITE CYCLE  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
t
WC  
AW  
CW  
BW  
AS  
WR  
WP  
DW  
DH  
Write Cycle Time  
12  
9
9
9
0
0
9
7
0
15  
10  
10  
10  
0
20  
12  
12  
12  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
t
Address Valid to End of Write  
Chip Select Low to End of Write  
Byte Enable Low to End of Write  
Address Set-up Time  
t
t
t
t
Address Hold from End of Write  
Write Pulse Width  
0
0
t
10  
8
12  
10  
0
t
Data Valid to End of Write  
Data Hold Time  
t
0
(1)  
OW  
____  
____  
____  
Write Enable High to Output in Low-Z  
1
1
1
t
___ _  
____  
____  
(1)  
WHZ  
Write Enable Low to Output in High-Z  
6
6
8
ns  
t
3210 tbl 10  
NOTE:  
1. This parameteris guaranteedwiththe ACLoad(Figure 2)bydevice characterization, butis notproductiontested.  
Timing Waveform of Read Cycle No. 1(1,2,3)  
tRC  
ADDRESS  
tAA  
tOH  
tOH  
DATAOUT VALID  
DATAOUT  
PREVIOUS DATAOUT VALID  
3210 drw 06  
,
NOTES:  
1. WE is HIGH for Read Cycle.  
2. Device is continuously selected, CS is LOW.  
3. OE, BHE, and BLE are LOW.  
6.42  
5