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SN54ALS165, Parallel-Load 8-Bit Registers
DEVICE STATUS: ACTIVE
PARAMETER NAME SN54ALS165
Voltage Nodes (V) 5
Vcc range (V)
Input Level
Output Level
Output
4.5 to 5.5
TTL
TTL
2S
FEATURES
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Complementary Outputs
l
l Direct Overriding Load (Data) Inputs
l Gated Clock Inputs
l Parallel-to-Serial Data Conversion
l Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK),
and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
DESCRIPTION
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The 'ALS165 are parallel-load 8-bit serial shift registers that, when clocked, shift the data
toward serial (Q and Q\ ) outputs. Parallel-in access to each stage is provided by eight
H
H
individual direct data (A-H) inputs that are enabled by a low level at the shift/load (SH/LD\)
input. The 'ALS165 have a clock-inhibit function and complemented serial outputs.
Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD\ is
held high and the clock inhibit (CLK INH) input is held low. The functions of CLK and CLK INH
are interchangeable. Since a low CLK and a low-to-high transition of CLK INH also
accomplishes clocking, CLK INH should be changed to the high level only while CLK is high.
Parallel loading is inhibited when SH/LD\ is held high. The parallel inputs to the register are
enabled while SH/LD\ is low independently of the levels of the CLK, CLK INH, or serial (SER)
inputs.
ROCHESTER [ Rochester Electronics ]
