RT6263A/B
Operation
VEN is held below a logic-low threshold voltage (VEN_L
)
The RT6263A/B is a high-efficiency, synchronous
step-down DC-DC converter that can deliver up to 3A
output current from a 4.5V to 17V input supply.
of the enable input (EN), the converter will disable
output voltage, that is, the converter is disabled and
switching is inhibited even if the VIN voltage is above
VIN under-voltage lockout threshold (VUVLO). During
shutdown mode, the supply current can be reduced to
ISHDN (10A or below). If the EN voltage rises above
the logic-high threshold voltage (VEN_H) while the VIN
voltage is higher than UVLO threshold, the device will
be turned on, that is, switching being enabled and
soft-start sequence being initiated. An internal resistor
REN_DN from EN to GND allows EN float to shutdown
the chip.
Advanced Constant On-Time Control and PWM
Operation
The RT6263A/B adopts ACOT® control for its ultrafast
transient response, low external component counts and
stable with low ESR MLCC output capacitors. When
the feedback voltage falls below the feedback
reference voltage, the minimum off-time one-shot
(200ns, typ.) has timed out and the inductor current is
below the current limit threshold, then the internal
on-time one-shot circuitry is triggered and the high-side
switch is turn-on. Since the minimum off-time is short,
the device exhibits ultrafast transient response and
enables the use of smaller output capacitance.
Soft-Start (SS)
The soft-start function is used to prevent large inrush
currents while the converter is being powered up. The
RT6263A/B provides an SS pin so that the soft-start
time can be programmed by selecting the value of the
external soft-start capacitor CSS connected from the
SS pin to GND. During the start-up sequence, the
soft-start capacitor is charged by an internal current
source ISS (typically, 6A) to generate a soft-start ramp
voltage, and the internal reference voltage follows this
slew rate. The out voltage can be built smoothly due to
the method described above, so the SS pin should not
be left unconnected to prevent overshoot voltage in
soft-start interval. After the SS pin voltage rises above
1.9V (typically) and VFB reaches 90% of reference
voltage, the open-drain output of PGOOD will be high
impedance to indicate power-good status. The typical
start-up waveform shown below indicates the
sequence and timing between the output voltage and
related voltage.
The on-time is inversely proportional to input voltage
and directly proportional to output voltage to achieve
pseudo-fixed frequency over the input voltage range.
After the on-time one-shot timer expired, the high-side
switch is turned off and the low-side switch is turned on
until the on-time one-shot is triggered again. To
achieve stable operation with low-ESR ceramic output
capacitors, an internal ramp signal is added to the
feedback reference voltage to simulate the output
voltage ripple.
Power Saving Mode (RT6263A Only)
The RT6263A automatically enters power saving mode
(PSM) at light load to maintain high efficiency. As the
load current decreases, the inductor current ripple
valley eventually touches the zero current, which is the
boundary between continuous conduction and
discontinuous conduction modes. The low-side switch
is turned off when the zero inductor current is detected.
In this case, the output capacitor is only discharged by
load current so that the switching frequency decreases.
As the result, the light-load efficiency can be enhanced
due to lower switching loss.
Enable Control
The RT6263A/B provides an EN pin, as an external
chip enable control, to enable or disable the device. If
Copyright © 2020 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
DS6263A/B-00 January 2020
www.richtek.com
5
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
