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RT5701GCP 参数 Datasheet PDF下载

RT5701GCP图片预览
型号: RT5701GCP
PDF下载: 下载PDF文件 查看货源
内容描述: [IC REG BUCK PROG 4A SYNC TSSOP]
分类和应用:
文件页数/大小: 24 页 / 310 K
品牌: RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
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RT5701  
Functional Pin Description  
Pin No.  
Pin Name  
Pin Function  
Nominal VOUT setting select input pin.  
VSEL = Low selects {0x11.ENSEL0, 0x11.VoutSEL0[6:0], 0x14.PWM0,  
0x1D.VOUT_BANK0[1:0]}.  
1
VSEL  
VSEL = High selects {0x10.ENSEL1, 0x10.VoutSEL1[6:0], 0x14.PWM1,  
0x1C.VOUT_BANK1[1:0]}.  
If 0x1C.VOUT_BANK1[1:0] 0x1D.VOUT_BANK0[1:0], do not toggle VSEL  
when EN = High.  
Enable Control Input. The IC enable control pin turns on the step-down  
converter if the internal register ENSEL bit = 1. If ENSEL = 0, EN goes high still  
cannot enable step-down converter. The EN pin includes a internal pull-down  
current about 1A. When IC protection occurs and is latched in shutdown state,  
toggling EN or re-power AVDD can reset the latch state.  
2
EN  
3
4
SCL  
I2C Interface Clock Input.  
GNDR  
VOUT  
NC  
Remote Ground Sense Input.  
Step-Down Converter Output Voltage Sense Input.  
No Internal Connection.  
5
6, 10  
13,15  
(Exposed Pad)  
Ground. The exposed pad must be soldered to a large PCB and connected to  
GND for maximum power dissipation.  
GND  
7
AVDD  
Analog and I2C Interface Power Input.  
8, 9  
11,12  
14  
PVIN  
LX  
Power Input. Input capacitor CIN must be placed as close to IC as possible.  
Switch Node.  
I2C Interface Data Input.  
SDA  
Functional Block Diagram  
AVDD  
PVIN  
VSEL  
UVLO  
Bias Supply  
Thermal  
Shutdown  
E-Fuse  
Bandgap  
DVS  
Current Limit Detect  
Gate Driver  
VREF  
EN  
Register File  
LX  
PWM Control Logic  
SCL  
SDA  
FB  
2
Soft-Start  
I C  
Negative Inductor  
Current Detect  
Oscillator  
GNDR  
VOUT  
GND  
Copyright 2015 Richtek Technology Corporation. All rights reserved.  
©
is a registered trademark of Richtek Technology Corporation.  
DS5701-01 July 2015  
www.richtek.com  
3