RT3667BL
Pin No.
Pin Name
IMONA
Pin Function
Current monitor output for the VDDNB controller. This pin outputs a
voltage proportional to the output current.
17
Processor memory interface power rail and serves as the reference for
PWROK, SVD, SVC and SVT. This pin is used by the VR to reference the
SVI pins.
18
19
VDDIO
System power good input. If PWROK is low, the SVI interface is disabled
and VR returns to BOOT-VID state with initial load line slope and initial
offset. If PWROK is high, the SVI interface is running and the DAC
decodes the received serial VID codes to determine the output voltage.
PWROK
20
21
22
23
24
SVC
SVD
SVT
Serial VID clock input from processor.
Serial VID data input from processor. This pin is a serial data line.
Serial VID telemetry input from VR. This pin is a push-pull output.
Over clocking offset setting for the VDD controller.
OFS
OFSA
Over clocking special purpose offset setting for the VDDNB controller.
1st platform setting. Platform can use this pin to set OCP_TDC threshold,
DVID compensation bit1 and internal ramp slew rate.
25
SET1
2st platform setting. Platform can use this pin to set quick response
threshold, OCP_TDC trigger delay time, DVID compensation bit0 and
over clocking offset enable setting.
26
SET2
Over current indicator for dual OCP mechanism. This pin is an open drain
output.
27
28
OCP_L
VCC
Controller power supply input. Connect this pin to 5V with an 1F or
greater ceramic capacitor for decoupling.
Internal bias current setting. Connect only a 100k resistor from this pin
to GND to generate bias current for internal circuit. Place this resistor as
close to IBIAS pin as possible.
29
IBIAS
30
31
COMPA
FBA
Compensation node of the VDDNB controller.
Output voltage feedback input of VDDNB controller. This pin is the
negative input of the error amplifier for the VDDNB controller.
VDDNB controller voltage sense input. This pin is connected to the
terminal of VDDNB controller output voltage.
32
VSENA
33, 36
34, 35
37
ISENA2P, ISENA1P Positive current sense input of Channel 1 and 2 for VDDNB controller.
ISENA2N, ISENA1N Negative current sense input of Channel 1 and 2 for VDDNB controller.
EN
Controller enable control input. A logic high signal enables the controller.
Power good indicator for the VDDNB controller. This pin is an open*drain
output.
38
39
PGOODA
Power good indicator for the VDD controller. This pin is an open-drain
output.
PGOOD
VDDNB controller on-time setting. Connect this pin to the converter input
voltage, VIN, through a resistor, RTONNB, to set the on-time of
UGATE_VDDNB and also the output voltage ripple of VDDNB controller.
40
TONSETA
41, 42
43, 51
PWMA2, PWMA1
BOOT1, BOOT2
PWM output for Channel 1 and 2 of VDDNB controller.
Bootstrap supply for high-side MOSFET. This pin powers high-side
MOSFET driver.
Copyright 2019 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS3667BL-00 September 2019
www.richtek.com
3
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
