RT3661AB
Operation
TM
Soft-Start and Slew-Rate Control
The RT3661AB adopts G-NAVP
(Green Native
AVP) which is Richtek's proprietary topology derived
from finite DC gain of EA amplifier with current mode
control, making it easy to set the droop to meet all
AMD CPU requirements of AVP (Adaptive Voltage
This block controls the slew rate of the internal
reference voltage when output voltage changes.
Error Amplifier
TM
Error amplifier generates COMP/COMP_NB signal by
the difference between VSET/VSET_NB and
FB/FB_NB.
Positioning). The G-NAVP controller is one type of
current mode constant on-time control with DC offset
cancellation. The approach can not only improve DC
offset problem for increasing system accuracy but
also provide fast transient response. When current
feedback signal reaches COMP signal, it generates
an on-time width to achieve PWM modulation.
Offset Cancellation
This block cancels the output offset voltage from
voltage ripple and current ripple to achieve accurate
output voltage.
MUX and ADC
UVLO
The MUX supports the inputs from SET1, TSEN,
TSEN_NB, IMONI, IMONI_NB, VSEN, VSEN_NB.
The ADC converts these analog signals to digital
codes for reporting or performance adjustment.
Detect the VCC pin voltage for under voltage lockout
protection and power on reset operation.
PWM CMP
The PWM comparator compares COMP signal
(COMP/COMP_NB) and current feedback signal to
generate a signal for TONGEN.
SVI2 Interface/Configuration Registers/Control
Logic
The SVI2 interface uses the SVC, SVD, and SVT pins
to communicate with CPU. The configuration
registers save the digital data from ADC output for
reporting or performance adjustment. The Control
Logic controls the ADC timing and generates the
digital code of the VID for VSEN/VSEN_NB voltage.
TONGEN
This block generates an on-time pulse which high
interval is based on the on-time setting.
RAMP
The Ramp generator is designed to improve noise
immunity and reduce jitter.
Loop Control Protection Logic
Loop control protection logic detects EN and UVLO
signals to initiate the soft-start function, and the
PGOOD and VRHOT_L will be controlled after the
soft-start is finished. When VRHOT indication event
occurs, the VRHOT_L pin voltage will be pulled low.
OC/OV/UV
Output voltage and output current are sensed for over
current, over voltage and under voltage protection.
DAC
The DAC receives VID codes from the SVI2 control
logic to generate an internal reference voltage
(VSET/VSET_NB) for controller.
Copyright © 2019 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
6
DS3661AB-05 May 2019
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
