M16C/62P Group (M16C/62P, M16C/62PT)
1.Overview
1.3
Block Diagram
Figure 1.1 is a M16C/62P Group (M16C/62P, M16C/62PT) 128-pin and 100-pin version Block Diagram,
Figure 1.2 is a M16C/62P Group (M16C/62P, M16C/62PT) 80-pin version Block Diagram.
8
8
8
8
8
8
8
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6
<VCC2 ports>(4)
<VCC1 ports>(4)
Internal peripheral functions
Timer (16-bit)
A/D converter
System clock
generation circuit
(10 bits X 8 channels
Expandable up to 26 channels)
XIN-XOUT
XCIN-XCOUT
PLL frequency synthesizer
On-chip oscillator
Output (timer A): 5
Input (timer B): 6
UART or
clock synchronous serial I/O
(8 bits X 3 channels)
Three-phase motor
control circuit
CRC arithmetic circuit (CCITT )
(Polynomial : X16+X12+X5+1)
Clock synchronous serial I/O
(8 bits X 2 channels)
M16C/60 series16-bit CPU core
Memory
ROM (1)
SB
R0H
R1H
R0L
R1L
Watchdog timer
(15 bits)
USP
ISP
R2
R3
RAM (2)
DMAC
(2 channels)
INTB
PC
FLG
A0
A1
FB
D/A converter
(8 bits X 2 channels)
Multiplier
<VCC1 ports>(4)
<VCC2 ports>(4)
Port P12 Port P13
Port P11
Port P14
(3)
(3)
(3)
(3)
8
2
8
8
NOTES :
1. ROM size depends on microcomputer type.
2. RAM size depends on microcomputer type.
3. Ports P11 to P14 exist only in 128-pin version.
4. Use M16C/62PT on VCC1= VCC2.
Figure 1.1
M16C/62P Group (M16C/62P, M16C/62PT) 128-pin and 100-pin version Block Diagram
Rev.2.41 Jan 10, 2006 Page 5 of 96
REJ03B0001-0241
RENESAS [ RENESAS TECHNOLOGY CORP ]
