VRS51L30xx High-Performance 8051 MCU + F-RAM
1 Instruction Set
Instr.
Size
Mnemonic
Description
Hex Code
(bytes)
Cycles
The following table describes the instruction set of the
VRS51L30xx. The instructions are binary code-compatible
and perform the same functions as industry standard
8051s.
Boolean Instruction
CLR C
CLR bit
SETB C
SETB bit
CPL C
Clear Carry bit
Clear bit
Set Carry bit to 1
Set bit to 1
Complement Carry bit
Complement bit
Logical AND between Carry and bit
Logical AND between Carry and not bit
Logical ORL between Carry and bit
Logical ORL between Carry and not bit
Copy bit value into Carry
Copy Carry value into Bit
1
2
1
2
1
2
2
2
2
2
2
2
1
4
1
4
1
4
4
4
4
4
4
3
C3h
C2h
D3h
D2h
B3h
B2h
82h
B0h
72h
A0h
A2h
92h
TABLE 3: LEGEND FOR INSTRUCTION SET TABLE
CPL bit
Symbol
A
Function
Accumulator
ANL C,bit
ANL C,#bit
ORL C,bit
ORL C,#bit
MOV C,bit
MOV bit,C
Rn
Register R0-R7
Direct
@Ri
Rel
Internal register address
Internal register pointed to by R0 or R1 (except MOVX)
Two's complement offset byte
Direct bit address
Bit
Data Transfer Instructions
#data
#data 16
addr 16
addr 11
8-bit constant
16-bit constant
16-bit destination address
11-bit destination address
MOV A, Rn
MOV A, direct
MOV A, @Ri
MOV A, #data
MOV Rn, A
Move register to A
Move direct byte to A
Move data memory to A
Move immediate to A
Move A to register
Move direct byte to register
Move immediate to register
Move A to direct byte
Move register to direct byte
Move direct byte to direct byte
Move data memory to direct byte
Move immediate to direct byte
Move A to data memory
1
2
1
2
1
2
2
3
E8h-EFh
E5h
E6h-E7h
74h
F8h-FFh
A8h-AFh
78h-7Fh
F5h
88h-8Fh
85h
3
D
2
1
3
2
3
3
3
3
3
2
3
2
3
TABLE 4: VRS51L30XX INSTRUCTION SET
MOV Rn, direct
MOV Rn, #data
MOV direct, A
MOV direct, Rn
MOV direct, direct
MOV direct, @Ri
MOV direct, #data
MOV @Ri, A
MOV @Ri, direct
MOV @Ri, #data
MOV DPTR, #data
MOVC A, @A+DPTR
MOVC A, @A+PC
MOVX
E
2
Instr.
Cycles
Size
2
2
3
2
3
1
2
2
3
Mnemonic
Description
Hex Code
(bytes)
Arithmetic instructions
ADD A, Rn
D
86h-87h
75h
Add register to A
1
2
28h-2Fh
ADD A, direct
ADD A, @Ri
ADD A, #data
ADDC A, Rn
ADDC A, direct
ADDC A, @Ri
ADDC A, #data
SUBB A, Rn
SUBB A, direct
SUBB A, @Ri
SUBB A, #data
INC A
INC Rn
INC direct
INC @Ri
DEC A
DEC Rn
DEC direct
DEC @Ri
INC DPTR
MUL AB
Add direct byte to A
Add data memory to A
Add immediate to A
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
2
1
1
1
1
1
3
3
2
2
3
3
2
2
3
3
2
2
2
3
3
2
2
3
3
2
2
25h
26h-27h
24h
38h-3Fh
35h
36h-37h
34h
98h-9Fh
95h
96h-97h
94h
04h
08h-0Fh
05h
06h-07h
S
F6h-F7h
A6h-A7h
76h-77h
90h
Move direct byte to data memory
N
Move immediate to data memory
Move immediate to data pointer
Add register to A with carry
Add direct byte to A with carry
Add data memory to A with carry
Add immediate to A with carry
Subtract register from A with borrow
Subtract direct byte from A with borrow
Subtract data mem from A with borrow
Subtract immediate from A with borrow
Increment A
Increment register
Increment direct byte
Increment data memory
Decrement A
Decrement register
Decrement direct byte
Decrement data memory
Increment data pointer
Multiply A by B
Divide A by B
Decimal adjust A
N
3+1
Move code byte relative DPTR to A
1
1
93h
E
Move code byte relative PC to A
3+1
83h
Move external data (A8) to A
1
3*
2*
E2h-E3h
A,{MPAGE, @Ri}
MOVX A, @DPTR
G
Move external data (A16) to A
1
E0h
M
I
MOVX
{MPAGE, @Ri},A
MOVX @DPTR, A
Move A to external data (A8)
1
2*
F2h-F3h
.
Move A to external data (A16)
1
2
2
1*
F0h
C0h
D0h
C8h-CFh
C5h
C6h-C7h
t
S
PUSH direct
M
POP direct
Push direct byte onto stack
Pop direct byte from stack
Exchange A and register
3
n
2
3
4
4
XCH A, Rn
1
e
2
14h
XCH A, direct
XCH A, @Ri
Exchange A and direct byte
E
18h-1Fh
O
15h
Exchange A and data memory
Exchange A and data memory
lower nibble
1
m
XCHD A, @Ri
1
4
D6h-D7h
16h-17h
A3h
D
e
Branching Instructions
ACALL addr 11
LCALL addr 16
RET
e
A4h
Absolute call to subroutine
c
2
3
1
1
2
3
2
2
2
3
3
3
1
2
2
3
3
3
3
2
3
4+1
5+1
3+1
3+1
2+1
3+1
3+1
3+1
3+1
3 / 4 +1
3 / 4 +1
3 / 4 + 1
2+1
3+1
3+1
4 / 5 +1
3 / 4 +1
3 / 4 +1
4 / 5 + 1
3 / 4 +1
3 / 4 +1
11h-F1h
12h
22h
32h
01h-E1h
02h
80h
40h
50h
20h
30h
10h
73h
60h
70h
B5h
B4h
C
DIV AB
DA A
Logical Instructions
ANL A, Rn
2
4
84h
D4h
Long call to subroutine
Return from subroutine
a
RETI
AJMP addr 11
Return fro
l
m interrupt
E
AND register to A
AND direct byte to A
AND data memory to A
AND immediate to A
AND A to direct byte
1
2
3
3
2
3
3
2
3
58h-5Fh
55h
56h-57h
54h
Absolute jump unconditional
p
ANL A, direct
ANL A, @Ri
ANL A, #data
ANL direct, A
ANL direct, #data
ORL A, Rn
ORL A, direct
ORL A, @Ri
ORL A, #data
ORL direct, A
ORL direct, #data
XRL A, Rn
XRL A, direct
XRL A, @Ri
XRL A, #data
XRL direct, A
XRL direct, #data
CLR A
2
1
2
2
3
1
2
1
2
2
3
1
W
LJMP addr 16
Long jump unconditional
SJMP rel
Short jump (relative address)
R
Jump on carry = 1
Jump on carry = 0
Jump on direct bit = 1
Jump on direct bit = 0
JC rel
r
52h
JNC rel
E
53h
AND immediate data to direct byte
OR register to A
JB bit, rel
JNB bit, rel
t
48h-4Fh
45
c
CJNE A, direct, rel
CJNE A, #d, rel
CJNE Rn, #d, rel
CJNE @Ri, #d, rel
DJNZ Rn, rel
OR direct byte to A
T
JBC bit, rel
Jump on direct bit = 1 and clear
Jump indirect relative DPTR
Jump on accumulator = 0
Jump on accumulator 1= 0
Compare A, direct JNE relative
Compare A, immediate JNE relative
Compare reg, immediate JNE relative
Compare ind, immediate JNE relative
Decrement register, JNZ relative
Decrement direct byte, JNZ relative
N
3
2
3
3
2
3
3
2
3
OR data memory to A
OR immediate to A
46h-47h
JMP @A+DPTR
e
JZ rel
r
44h
42h
43h
OR A to direct byte
JNZ rel
i
OR immediate data to direct byte
O
d
Exclusive-OR register to A
68h-6Fh
65h
66h-67h
R
Exclusive-OR direct byte to A
Exclusive-OR data memory to A
Exclusive-OR immediate to A
2
1
2
2
3
1
1
1
1
1
1
1
B8h-BFh
B6h-B7h
D8h-DFh
D5
o
N
64h
62h
63h
E4h
F4h
C4h
23h
33h
03h
13h
Exclusive-OR A to direct byte
O
DJNZ direct, rel
Miscellaneous Instruction
NOP
NOP
N
Exclusive-OR immediate to direct byte
3
Clear A
1
1
1
1
1
1
1
No operation
If PCON.4 is 0 (reset Value): NOP
If MSB (@RamPtr) == 0
Accumulator value is written
in SFR{1,@RamPtr[6:0]}
If MSB (@RamPtr) == 1
SFR{1,@RamPtr[6:0]}
1
1
1
1
00h
A5h
CPL A
SWAP A
RL A
RLC A
RR A
Compliment A
F
Swap nibbles of A
Rotate A left
MOV @RamPtr,A
MOV A,@RamPtr
2
3
3
4
A5h
A5h
Rotate A left through carry
Rotate A right
RRC A
Rotate A right through carry
is written in Accumulator
Definitions
Notes on number of Cycles:
Rn:
Any of the register R0 to R7
@Ri:
#data:
#data16:
bit:
Indirect addressing using Register R0 or R1
immediate Data provided with Instruction
Immediate data included with instruction
address at the bit level
“X / Y” cycles denotes number of cycle Without / With Jump
“+1” indicates extra Cycle that may be required because of Flash access
rel:
relative address to Program counter from +127 to –128
Addr11: 11-bit address range
Addr16: 16-bit address range
#d:
Immediate Data supplied with instruction
Rev. 2.3
August 2011
page 6 of 116
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
