VRS51L30xx High-Performance 8051 MCU + F-RAM
VRS51L30xx (MLF-68) Pin Description
TABLE 2: VRS51L30XX PIN DESCRIPTIONS FOR MLF-68 PACKAGE
MLF-
68
MLF-
68
Name
XTAL1
I/O
Function
Name
I/O
I/O
Function
O
Crystal Oscillator (Output)
Port 4.6
P1.5
SDO
P1.6
SCK
SCL*
Port 1.5
26
1
P4.6
I/O
I
O
SPI Data output
Port 1.6
XTAL2
P4.7
Crystal Oscillator (Input)
Port 4.7
I/O
O
27
28
29
I/O
GND
I/O
O
SPI Clock
2
VSS
Device ground
Port 4.0
I/O
I
I²C Clock (Alternate Pin)
Pulse Counter PC1 input 3
Port P1.7
P4.0
PC1.3
P1.7
T1OUT
P2.0
Timer 1 Output
Port 2.0
I/O
I
I/O
O
3
4
5
SDI
SPI Data Input
I²C Data (Alternate Pin)
Reset
30
31
32
PWM0
A8
PWM0 Output
Ext. Address Bus A8
Port 2.1
SDA*
RESET
P3.0
I/O
I
O
P2.1
I/O
O
I/O
I
Port 3.0
PWM1
A9
PWM1 Output
Ext. Address Bus A9
Port 2.2
RXD0
PC0.1
P4.5
UART0 RX pin
Pulse Counter PC0 input 1
Port 4.5
O
I
D
P2.2
I/O
O
I/O
O
6
7
PWM2
A10
PWM2 Output
Ext. Address Bus A10
T0OUT
P5.0
Timer 0 output
O
I/O
O
Port 5.0
E
P2.3
I/O
O
Port 2.3
PWM0*
P5.1
PWM0 Output (Alternate Pin)
Port 5.1
PWM3
TXD0*
A11
PWM3 Output
I/O
O
33
34
8
O
UART0 TX pin (Alternate Pin )
PWM1*
P5.2
PWM1 Output (Alternate Pin)
Port 5.2
D
O
Ext. Address Bus A11
Port 2.4
I/O
O
9
P2.4
I/O
O
S
PWM2*
P5.3
PWM2 Output (Alternate Pin)
Port 5.3
PWM4
RXD0*
PC0.2
A12
PWM4 Output
N
I/O
O
10
I
UART0 RX pin (Alternate Pin)
Pulse Counter PC0 input 2
Ext. Address Bus A12
PWM3*
VSS
PWM3 Output (Alternate Pin)
Device ground
N
I
11
12
GND
GND
I/O
O
E
O
VSS
Device ground
DBCS0
O
Ext. Data bus DBCS0
P3.1
Port 3.1
13
G
P2.5
I/O
O
Port 2.5
TXD0
P3.2
UART0 TX pin
PWM5
PWM5 output
M
I
I/O
I
Port 3.2
35
T1EX
A13
I
Timer 1 EX input
14
INT0
Interrupt 0 input
Pulse Counter PC0 input 0
Port 3.3
.
t
O
Ext. Address Bus A13
PC0.0
P3.3
I
S
DBCS1
O
Ext. Data bus DBCS1
I/O
M
n
P2.6
I/O
Port 2.6
15
16
INT1
I
Interrupt 1 input
PWM6
T0EX
A14
O
PWM6 output
e
PC1.0
P3.4
I
Pulse Counter PC1 input 0
Port 3.4
E
36
I
Timer 0 EX input
I/O
O
E
O
Ext. Address Bus A114
m
SCL
I/O
I²C clock
DBCS2
P2.7
O
Ext. Data bus DBCS2
D
T0IN
I
Timer 0 Input
e
I/O
O
I
Port 2.7
C
PC0.3
EXBR0
P3.5
I
Pulse Counter PC0 input 3
UART0 External Baud Rate Input
Port 3.5
c
PWM7
TCK
PWM7 output
I
37
JTAG TCK input
Ext. Data bus DBCS3
Port 4.1
a
I/O
I/O
I
l
E
DBCS3
P4.1
O
SDA
I²C Data
17
I/O
p
W
T1IN
Timer 1 Input
38
TMS
I
JTAG TMS Input
JTAG Program mode
Ext Address Latch Enable
Port 4.2
EXBR1
P3.6
I
UART1 External Baud Rate input
R
e
CM0
ALE
I
r
I/O
Port 3.6
39
O
I/O
O
I/O
I
18
19
Ext Data memory access write signal
(active low)
WR
P3.7
RD
O
t
P4.2
40
I/O
O
Port 3.7
c
TDO
P4.3
TDI
JTAG TDO Line
T
Ext Data memory access read signal (active
N
Port 4.3
low)
e
41
JTAG TDI line
20
21
VDD
VDD
Positive supply
r
i
TXD1*
T1EX
RXD1*
T0EX
PC1.2
P6.7
A7
O
I
UART1 TX pin (Alternate Pin)
Timer 1 EX input
UART1 RX pin (Alternate Pin)
Timer 0 EX input
Pulse Counter PC1 input 2
Port 6.7
VDD
VDD
O
I/O
Positive supply
Port 5.4
42
d
P5.4
22
23
24
25
R
I
PWM4*
O
PWM4 Output (Alternate Pin)
Port 5.5
43
I
P5.5
I/O
O
o
N
I
PWM5*
PWM5 Output (Alternate Pin)
O
N
I/O
O
I/O
O
I/O
O
P5.6
I/O
O
Port 5.6
44
45
46
Ext. Address 7 (Non-Multiplexed mode)
Port 6.6
PWM6*
P5.7
PWM6 Output (Alternate Pin)
P6.6
A6
I/O
O
Port 5.7
F
Ext. Address 6 (Non-Multiplexed mode)
Port 6.5
PWM7*
PWM7 Output (Alternate Pin)
P6.5
A5
Ext. Address 5 (Non-Multiplexed mode)
Rev. 2.3
August 2011
page 4 of 116
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
