VRS51C1000
VRS51C1000 ISPVx Firmware boot program
System Control Register
An ISP boot loader program is available for the
VRS51C1000 (ISPVx Firmware, x = revision, see
Ramtron website for latest revision).
By default upon reset, the IAP feature of the
VRS51C1000 is de-activated. The IAPE bit of the
SYSCON register is used to enable (and disable) the
VRS51C1000 IAP function.
The ISPVx Firmware enables In-System-Programming
of the VRS51C1000 on the final application PCB using
the device’s UART interface. See the following figure
TABLE 6: SYSTEM CONTROL REGISTER (SYSCON) – SFR BFH
for
a
hardware configuration example.
Other
7
6
5
4
3
2
1
0
ALEI
configurations are also possible.
XRAME
WDR
Unused
IAPE
FIGURE 4: VRS51C1000 INTERFACE FOR IN-SYSTEM PROGRAMMING
Bit
Mnemonic Description
7
WDR
This is the Watchdog Timer reset bit. It will
be set to 1 when the reset signal generated
by WDT overflows.
-
-
-
VRS51C1000
(with ISPV2
Firmware)
6
5
4
3
2
1
0
Unused
Unused
Unused
Unused
IAPE
TXD
RXD
-
To PC
IAP function enable bit
XRAME
ALEI
768 byte on-chip enable bit
ALE output inhibit bit, which is used to
reduce EMI.
Creset
PNP
150k
RES
IAP Flash Address and Data Registers
Rreset
The IAPFADHI and IAPADLO registers are used to
specify the address at which the IAP function will be
performed.
See Ramtron’s website in order to download the
“Versa Ware ISP” Window’s™ application which allows
communication with the ISPVx firmware.
TABLE 7:IAP FLASH ADDRESS HIGH - SFR F4H
7
6
5
4
3
2
2
1
1
0
0
IAPFADHI[15:8]
The VRS51C1000 can be ordered with or without the
ISPVx bootloader firmware (see Ordering information
section of this Datasheet for part number information).
TABLE 8:IAP FLASH ADDRESS LOW - SFR F5H
7
6
5
4
3
IAPFADLO[15:8]
The ISPVx bootloader firmware can also be
programmed into the VRS51C1000 by the user.
Source code is included with the Versa Ware ISP
application software.
The IAPFDATA SFR register contains the Data byte
required to perform the IAP function.
TABLE 9:IAP FLASH DATA REGISTER - SFR F6H
7
6
5
4
3
2
1
0
For more information on the ISPVx firmware, please
consult the “VRS51C1000 ISPVx Firmware User
Guide.pdf” available on the Ramtron web site.
IAPFDATA[7:0]
IAP Flash Control Register
VRS51C1000 IAP feature
The VRS51C1000 IAP function operation is controlled
by the IAP Flash Control register, IAPFCTRL.
The VRS51C1000 IAP feature refers to the ability of
the processor to self-program the Flash memory from
within the user program.
Setting the IAPSTART bit to 1, starts the execution of
the IAP command specified by the IAPFCT[1:0] bits of
the IAP Flash Control register.
Five SFR registers serve to control the IAP operation.
The description of these registers is provided below.
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