Industrial Temperature
16Mbit Enhanced Synchronous DRAM
1Mx16 ESDRAM
Preliminary Data Sheet
Clock and Clock Enable Parameters
Symbol
Parameter
-7.5
-10
Units
Notes
Min
7.5
15
2.8
5
Max
Min
10
20
3.5
6
Max
tCK2
Clock Cycle Time, CL = 2, 3
Clock Cycle Time, CL = 1
133MHz
100MHz
ns
ns
ns
ns
ns
ns
ns
ns
tCK1
66MHz
50MHz
tCKH2, tCKL2
tCKH1, tCKL1
tCKES
Clock High & Low Times, CL=2, 3
Clock High & Low Times, CL=1
Clock Enable Set-Up Time
-
-
-
-
1
1
2
-
2.5
1
-
tCKEH
Clock Enable Hold Time
1
-
-
tCKESP
tT
CKE Set-Up Time (Power down mode)
Transition Time (Rise and Fall)
2
-
2.5
-
-
-
4
4
Notes:
1. Assumes clock rise and fall times are equal to 1ns. If rise or fall time exceeds 1ns, other AC timing parameters must be compensated by an
additional [(trise+tfall)/2-1] ns.
Common Parameters
Symbol
Parameter
-7.5
-10
Units
Notes
Min
2.3
1
Max
Min
2.8
1
Max
tCS
Command and Address Set-Up Time
Command and Address Hold Time
RAS to CAS Delay Time
-
-
ns
ns
tCH
-
-
tRCD
tRC
tRAS
tRP
15
42
22.5
15
15
7.5
2
-
20
50
30
20
20
10
2
-
ns
Bank Cycle Time
120K
120K
ns
Bank Active Time
120K
120K
ns
Precharge Time
-
-
-
-
-
-
-
-
ns
tRRD
tCCD
tMRD
Bank to Bank Delay Time (Alt. Bank)
CAS to CAS Delay Time (Same Bank)
Mode Register Set to Active Delay
ns
ns
CLK
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
1999 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Page 6 of 9
Revision 1.0
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
