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SM2404T-10I 参数 Datasheet PDF下载

SM2404T-10I图片预览
型号: SM2404T-10I
PDF下载: 下载PDF文件 查看货源
内容描述: [Cache DRAM, 1MX16, 6ns, CMOS, PDSO50, TSOP2-50]
分类和应用: 动态存储器光电二极管内存集成电路
文件页数/大小: 9 页 / 110 K
品牌: RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
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Industrial Temperature  
16Mbit Enhanced Synchronous DRAM  
1Mx16 ESDRAM  
Preliminary Data Sheet  
Pin Descriptions  
Symbol  
CLK  
Type  
Input  
Input  
Function  
Clocks: All SDRAM input signals are sampled on the positive edge of CLK.  
CKE  
Clock Enable: CKE activates (high) or deactivates (low) the CLK signals. Deactivating the  
clock initiates the Power-Down and Self-Refresh operations (all banks idle), or Clock  
Suspend operation. CKE is synchronous until the device enters Power-Down and Self-  
Refresh modes where it is asynchronous until the mode is exited.  
/CS  
Input  
Input  
Chip Select: /CS enables (low) or disables (high) the command decoder. When the  
command decoder is disabled, new commands are ignored but previous operations  
continue.  
/RAS, /CAS,  
/WE  
Command Inputs: Sampled on the rising edge of CLK, combinations of these inputs define  
the command to execute.  
A11 (BS)  
A0-A10  
Input  
Input  
Selects bank to activate. A11 low selects Bank A and A11 high selects Bank B.  
Address Inputs: A0-A10 define the row address during the Bank Activate command. A0-  
A9 define the column address during Read and Write commands. A10/AP invokes the  
auto-precharge operation. During manual Precharge commands, A10/AP low specifies a  
single bank precharge while A10/AP high precharges all banks. The address inputs are  
also used to program the Mode Register.  
DQ0-DQ15  
Input/  
Data I/O: Data bus inputs and outputs. For Write cycles, input data is applied to these  
pins and must be set-up and held relative to the rising edge of clock. For Read cycles, the  
device drives output data on these pins after the CAS latency is satisfied.  
Output  
UDQM,  
LDQM  
Input  
Data I/O Mask Inputs: DQM inputs mask write data (zero latency) and act as a  
synchronous output enable (2-cycle latency) for read data.  
VDD  
Supply  
Supply  
Supply  
-
Power Supply for the input buffers and core logic: +3.3 V  
Power Supply for the output buffers: +3.3 V or +2.5V  
Ground: VSS and VSSQ are connected inside the chip.  
No connect - open pin.  
VDDQ  
VSS, VSSQ  
NC  
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921  
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com  
1999 Enhanced Memory Systems. All rights reserved.  
The information contained herein is subject to change without notice.  
Revision 1.0  
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