FM3135 Integrated RTC/Alarm/FRAM & Embedded Crystal
VBC bit (register 0Eh, bit 2) is set to a ‘1’, the VBAK
pin will source approximately 80 µA until VBAK
reaches VDD. This charges the capacitor to VDD
without an external diode and resistor charger.
There is a Fast Charge mode which is enabled by the
FC bit (register 0Eh, bit 1). In this mode the trickle
charger current is set to approximately 1 mA,
allowing a large backup capacitor to charge more
quickly.
•
In the case where no battery is used, the VBAK
pin should be tied to VSS.
! Note: systems using lithium batteries should clear
the VBC bit to 0 to prevent battery charging. The
VBAK circuitry includes an internal 1 KΩ series
resistor as a safety element. The trickle charger is UL
Recognized.
512 Hz or
SW out
/OSCEN
Oscillator
W
32.768 kHz
crystal
Clock
Divider
Update
Logic
1 Hz
Date
6 bits
Years
8 bits
Months
5 bits
CF
Hours
6 bits
Minutes
7 bits
Seconds
7 bits
Days
3 bits
R
User Interface Registers
Figure 2. Real-Time Clock Core Block Diagram
clock will have a maximum error of
±
2.17 ppm or
Calibration
±
0.09 minutes per month at the calibrated
When the CAL bit in register 00h is set to ‘1’, the
clock enters calibration mode. In calibration mode,
the ACS output pin is dedicated to the calibration
function and the power fail output is temporarily
unavailable. Calibration operates by applying a
digital correction to the counter based on the
frequency error. In this mode, the ACS pin is driven
with a 512 Hz (nominal) square wave. Any measured
deviation from 512 Hz translates into a timekeeping
error. The user converts the measured error in ppm
and writes the appropriate correction value to the
calibration register. The correction factors are listed
in the table below. Positive ppm errors require a
negative adjustment that removes pulses. Negative
ppm errors require a positive correction that adds
pulses. Positive ppm adjustments have the CALS
(sign) bit set to ‘1’, whereas negative ppm
adjustments have CALS = 0. After calibration, the
temperature.
The calibration setting is battery-backed and must be
reloaded should the backup source fail. It is accessed
with bits CAL.4-0 in register 01h. This value only
can be written when the CAL bit is set to a ‘1’. To
exit the calibration mode, the user must clear the
CAL bit to a ‘0’. When the CAL bit is ‘0’, the ACS
pin will revert to another function as defined in
Table 3. Control Bit Settings for ACS Pin.
Rev. 1.2
Feb. 2009
Page 4 of 21
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
