Overview
Serial Peripheral Interface – SPI Bus
The FM25CL04 is a serial FRAM memory. The
memory array is logically organized as 512 x 8 and is
accessed using an industry standard Serial Peripheral
Interface or SPI bus. Functional operation of the
FRAM is similar to serial EEPROMs. The major
difference between the FM25CL04 and a serial
EEPROM with the same pinout is the FRAM’s
superior write performance and power consumption.
The FM25CL04 employs
a
Serial Peripheral
Interface (SPI) bus. It is specified to operate at speeds
up to 20 MHz. This high-speed serial bus provides
high performance serial communication to a host
microcontroller. Many common microcontrollers
have hardware SPI ports allowing a direct interface.
It is quite simple to emulate the port using ordinary
port pins for microcontrollers that do not. The
FM25CL04 operates in SPI Mode 0 and 3.
Memory Architecture
The SPI interface uses a total of four pins: clock,
data-in, data-out, and chip select. It is possible to
connect the two data pins together. Figure 2
illustrates a typical system configuration using the
FM25CL04 with a microcontroller that offers an SPI
When accessing the FM25CL04, the user addresses
512 locations of 8 data bits each. These data bits are
shifted serially. The addresses are accessed using the
SPI protocol, which includes a chip select (to permit
multiple devices on the bus), an op-code, and an
address. The upper address bit is included in the op-
code. The complete address of 9-bits specifies each
byte address uniquely.
port. Figure 3 shows a similar configuration for a
D
microcontroller that has no hardware support for the
SPI bus.
E
Protocol Overview
D
Most functions of the FM25CL04 either are
controlled by the SPI interface or are handled
automatically by on-board circuitry. The access time
for memory operation is essentially zero, beyond the
time needed for the serial protocol. That is, the
memory is read or written at the speed of the SPI bus.
Unlike an EEPROM, it is not necessary to poll the
device for a ready condition since writes occur at bus
speed. So, by the time a new bus transaction can be
shifted into the device, a write operation will be
complete. This is explained in more detail in the
The SPI interface is a synchronous serial interface
S
using clock and data pins. It is intended to support
N
multiple devices on the bus. Each device is activated
N
using a chip select. Once chip select is activated by
the bus master, the FM25CL04 will begin monitoring
G
the clock and data lines. The relationship between the
ME
I
falling edge of /CS, the clock and data is dictated by
the SPI mode. The device will make a determination
of the SPI mode on the falling edge of each chip
S
M
select. While there are four such modes, the
E
FM25CL04 supports modes 0 and 3. Figure 4 shows
O
interface section.
the required signal relationships for modes 0 and 3.
D
For both modes, data is clocked into the FM25CL04
C
Users expect several obvious system benefits from
the FM25CL04 due to its fast write cycle and high
endurance as compared with EEPROM. In addition
there are less obvious benefits as well. For example
in a high noise environment, the fast-write operation
is less susceptible to corruption than an EEPROM
on the rising edge of SCK and data is expected on the
first rising edge after /CS goes active. If the clock
begins from a high state, it will fall prior to beginning
data transfer in order to create the first rising edge.
E
W
R
E
The SPI protocol is controlled by op-codes. These
op-codes specify the commands to the device. After
/CS is activated the first byte transferred from the bus
master is the op-code. Following the op-code, any
addresses and data are then transferred.
T
since it is completed quickly. By contrast, an
N
EEPROM requiring milliseconds to write is
vulnerable to noise during much of the cycle.
O
R
Note that the FM25CL04 contains no power
management circuits other than a simple internal
N
O
Certain op-codes are commands with no subsequent
data transfer. The /CS must go inactive after an
operation is complete and before a new op-code can
be issued. There is one valid op-code only per active
chip select.
power-on reset. It is the user’s responsibility to
F
ensure that VDD is within datasheet tolerances to
prevent incorrect operation.
Rev. 3.1
May 2005
Page 3 of 12
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
