WP
CS
Instruction Decode
Clock Generator
Control Logic
HOLD
SCK
Write Protect
128 x 32
FRAM Array
Instruction Register
9
8
Address Register
Counter
D
SI
SO
Data I/O Register
E
3
D
S
Nonvolatile Status
N
ME
Register
N
G
I
Figure 1. Block Diagram
S
M
E
Pin Descriptions
O
Pin Name
/CS
I/O
Input
Description
D
C
Chip Select: This active low input activates the device. When high, the device enters
low-power standby mode, ignores other inputs, and all outputs are tri-stated. When
low, the device internally activates the SCK signal. A falling edge on /CS must occur
E
W
prior to every op-code.
R
SCK
Input
Input
Serial Clock: All I/O activity is synchronized to the serial clock. Inputs are latched on
the rising edge and outputs occur on the falling edge. Since the device is static, the
clock frequency may be any value between 0 and 20 MHz and may be interrupted at
E
T
N
any time.
/HOLD
Hold: The /HOLD pin is used when the host CPU must interrupt a memory operation
er task. When /HOLD is low, the current operation is suspended. The device
ignores any transition on SCK or /CS. All transitions on /HOLD must occur while
O
for anoth
R
N
SCK is low.
O
/WP
SI
Input
Write Protect: This active low pin prevents write operations to the memory array or
F
the status register. A complete explanation of write protection is provided below.
Serial Input: All data is input to the device on this pin. The pin is sampled on the
rising edge of SCK and is ignored at other times. It should always be driven to a valid
logic level to meet IDD specifications.
Input
* SI may be connected to SO for a single pin data interface.
Serial Output: This is the data output pin. It is driven during a read and remains tri-
stated at all other times including when /HOLD is low. Data transitions are driven on
the falling edge of the serial clock.
SO
Output
* SO may be connected to SI for a single pin data interface.
Power Supply (2.7V to 3.65V)
Ground
VDD
VSS
Supply
Supply
Rev. 3.1
May 2005
Page 2 of 12