FM24C04C
No
Start
S
Address
Acknowledge
By Master
By F-RAM
Stop
Slave Address
1
A
Data Byte
Data
1
P
Acknowledge
Figure 7. Current Address Read
No
Acknowledge
Start
S
Address
Acknowledge
By Master
By F-RAM
Stop
Slave Address
1
A
Data Byte
A
Data Byte
1
P
Acknowledge
Data
Figure 8. Sequential Read
No
Address
Acknowledge
Start
Start
S
Address
Acknowledge
A
By Master
Stop
S
Slave Address
0
A
Word Address
A
Slave Address
1
A
Data Byte
Data Byte
1 P
By F-RAM
Acknowledge
Data
Figure 9. Selective (Random) Read
the beginning of a new row. Endurance can be
optimized by ensuring frequently accessed data is
located in different rows. Regardless, F-RAM read
and write endurance is effectively unlimited at the
1MHz two-wire speed. Even at 3000 accesses per
second to the same row, 10 years time will elapse
before 1 trillion endurance cycles occur.
Endurance
The FM24C04C internally operates with a read and
restore mechanism. Therefore, endurance cycles are
applied for each read or write cycle. The memory
architecture is based on an array of rows and
columns. Each read or write access causes an
endurance cycle for an entire row. In the FM24C04C,
a row is 64 bits wide. Every 8-byte boundary marks
Rev. 1.1
June 2011
Page 7 of 12
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
