FM18L08
A second design consideration relates to the level of
VDD during operation. Battery-backed SRAMs are
forced to monitor VDD in order to switch to battery
backup. They typically block user access below a
certain VDD level in order to prevent loading the
battery with current demand from an active SRAM.
The user can be abruptly cut off from access to the
memory in a power down situation without warning.
power cycles assuming the MCU/MPU pin tri-states
during the reset condition. The pullup resistor value
should be chosen to ensure the /CE pin tracks VDD yet
a high enough value that the current drawn when /CE
is low is not an issue.
VDD
FM18L08
R
FRAM memories do not need this system overhead.
The memory will not block access at any VDD level.
The user, however, should prevent the processor from
accessing memory when VDD is out-of-tolerance. The
common design practice of holding a processor in
reset during powerdown may be sufficient. It is
recommended that Chip Enable is pulled high and
allowed to track VDD during powerup and powerdown
cycles. It is the user’s responsibility to ensure that
chip enable is high to prevent accesses below VDD
min. (3.0V). Figure 3 shows an external pullup
resistor on /CE which will keep the pin high during
CE
MCU/
MPU
WE
OE
A(14:0)
DQ
Figure 3. Use of Pullup Resistor on /CE
Rev. 3.4
July 2007
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RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
