A10-A14
Block Decoder
32,768 x 8 FRAM Array
Column Decoder
Address
Latch
A0-A14
A0-A7
Row
Decoder
CE
A8-A9
Control
Logic
WE
OE
I/O Latch
Bus Driver
DQ0-7
Figure 1. Block Diagram
Pin Description
Pin Name
Type
Pin Description
A0-A14
Input
Address: The 15 address lines select one of 32,768 bytes in the FRAM array. The
address value is latched on the falling edge of /CE.
DQ0-7
/CE
I/O
Input
Data: 8-bit bi-directional data bus for accessing the FRAM array.
Chip Enable. /CE selects the device when low. Asserting /CE low causes the address
to be latched internally. Address changes that occur after /CE goes low will be
ignored until the next falling edge occurs.
/OE
Input
Input
Output Enable: Asserting /OE low causes the FM18L08 to drive the data bus when
valid data is available. Deasserting /OE high causes the DQ pins to be tri-stated.
Write Enable: Asserting /WE low causes the FM18L08 to write the contents of the
data bus to the address location latched by the falling edge of /CE.
/WE
VDD
VSS
Supply Supply Voltage
Supply Ground
Functional Truth Table
/CE
H
↓
L
L
/WE
Function
Standby/Precharge
Latch Address (and Begin Write if /WE=low)
Read
X
X
H
↓
Write
Note: The /OE pin controls only the DQ output buffers.
This product conforms to specifications per the terms of the Ramtron
standard warranty. The product has completed Ramtron’s internal
qualification testing and has reached production status.
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
http://www.ramtron.com
Rev. 3.4
July 2007
2 of 13
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
