P4C1041
AC TEST COꢁDITIOꢁS
Input Pulse Levels
GND to 3.0V
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Value
Output Load
3ns
1.5V
1.5V
See Figures 1 & 2
Figure 1. Output Load
Figure 2. Thevenin Equivalent
* including scope and test fixture.
ꢁote:
Becauseoftheultra-highspeedoftheP4C1041,caremustbetakenwhen
testing this device; an inadequate setup can cause a normal functioning
part to be rejected as faulty. Long high-inductance leads that cause
supply bounce must be avoided by bringing the VCC and ground planes
directly up to the contactor fingers. A 0.01 µF high frequency capacitor
is also required between VCC and ground. To avoid signal reflections,
proper termination must be used; for example, a 50Ω test environment
should be terminated into a 50Ω load with 1.73V (Thevenin Voltage) at
the comparator input, and a 116Ω resistor must be used in series with
DOUT to match 166Ω (Thevenin Resistance).
TRꢀTH TABLE
Mode
CE
H
L
OE
ꢀ
L
WE
ꢀ
BLE
ꢀ
BHE
ꢀ
I/O0 - I/O7
High Z
DOUT
I/O8 - I/O15
High Z
DOUT
Power
Standby
Active
Active
Active
Active
Active
Active
Active
Powerdown
Read All Bits
H
H
H
L
L
L
Read Lower Bits Only
Read Upper Bits Only
Write All Bits
L
L
L
H
L
DOUT
High Z
DOUT
L
L
H
L
High Z
DIN
L
ꢀ
ꢀ
ꢀ
H
L
DIN
Write Lower Bits Only
Write Upper Bits Only
Selected, Outputs Disabled
L
L
L
H
L
DIN
High Z
DIN
L
L
H
ꢀ
High Z
High Z
L
H
ꢀ
High Z
Document # SRAM133 REV B
Page 7 of 10
PYRAMID [ PYRAMID SEMICONDUCTOR CORPORATION ]
