PACE 1757 M/ME
40 MHz
SIGNAL PROPAGATION DELAYS (cont'd)
20 MHz
30 MHz
35 MHz
Symbol
TD/I(EXT ADR)V
TSTRBD(EXT ADR ER) External Address Error
TIBDV(EDC GEN)V
TC(GNT)
Description
MMU Cache Hit
MIN
MAX MIN MAX MIN
MAX
23
18
24
22
21
28
43
18
20
42
33
33
20
27
25
23
12.5
19
20
21
15
15
18
18
18
23
MIN
MAX
23
16
23
18
17
25
40
16
18
40
30
30
20
23
25
21
11.5
16
19
20
12
12
15
15
15
20
25
25
30
35
30
34
50
25
25
40
40
25
25
32
30
28
16
28
29
31
24
24
26
26
26
30
23
20
25
25
25
30
45
20
22
45
35
35
20
30
25
24
13
22
21
22
18
18
20
20
20
25
Error Correction Write Cycle
Arbiter Priority Transition
Address Ready
TC(RDYA)
TIBDIN(MEM PAR ER) Parity Mode
TC(MEM PRT ER)
Memory Protect Error
T
Write Protect Cache Hit
Write Protect Cache Miss
Cache Hit (BPU Protection Error)
Cache Hit (MMU Key-Lock Error)
Cache Hit (BPU Protection Error)
Cache Hit (MMU Key-Lock Error)
Clock to EXT Address Valid (Miss)
Clock to EXT Address Valid (Miss)
Ready Data
Ready Data
Ready Data
Address Valid
Address Valid
Read Strobes
Read Strobes
Write Strobes
Write Strobes
Start-Up ROM
Timer Clock
Extended Address Set-Up
Edge Sensitive Pulse Width
Clock Rise and Fall Time
STRBD (WR PROT)
TC(WR PROT)I
TD/I(PROT FLAG)
TD/I(PROT FLAG)
TC(PROT FLAG)
TC(PROT FLAG)
TC(EXT ADR)V
TFC(IB OUT)V
T
(RDYD)
(RDYD)
EX RDY1
T
EX RDY
TC (RDYD)V
TSTRBAh(A)V
TIBAV(A)V
TFC (R)L
TSTRBDH(R)H
TSTRBDH(W)L
TSTRBDL(W)H
TSTRBD(STRTROM)
TC(TIMCLK)
TEXT AD(FC B3)
TF(F), TI(I)
10
5
10
5
10
5
10
5
tr, tf
5
5
5
5
Units = ns
Note
All timing parameters are composed of Three elements. The first "T" stands for timing. The second represents the "from" signal. The third in
parentheses indicates "to" signal. When the CPU clock is one of the signal elements, either the rising edge "E" or the fallingedge "FC" is referenced.
When other elements are used, an additional suffix indicates the final logic level of the signal. "L" - low level, "H" - high level, "V" - valid, "Z" - high
impedance, "X" - don't care, "LH" - low to high, "ZH" - high impedance to high, "R" - read cycle, and "W" - write cycle.
Do c um e nt # MICRO-10 REV B
Pa g e 9 o f 34
PYRAMID [ PYRAMID SEMICONDUCTOR CORPORATION ]
