PACE 1757 M/ME
DIFFERENCES BETWEEN THE PACE1757M AND PACE1757ME
The PACE1757ME, which uses the P1750AE CPU, achieves a 41% boost in performance (in clock cycles) over the
PACE1757M, which uses the P1750A CPU. This reduction in clocks per instruction is because of three architectural
enhancements:
1. The inclusion of a 24 x 24 Multiply Accumulate (MAC) array.
2. A reduction in non-bus cycles to 2 clocks (bus cycles remain at 4 clocks to maintain full compatibility with CPU's peripheral
chips).
3. Branch calculation logic.
The table below shows how the MAC improves all multiply operations - both integer and floating point - by 477% to 760%
PACE1750AE
PACE1750A
Gain
# Clocks
(%)
Execution
Execution
Instruction
Clocks
Time
Clocks
Time
(40 MHz)
(40 MHz)
Integer Add/Sub
4
6
100ns
150ns
100ns
225ns
450ns
850ns
225ns
425ns
200ns
100ns
675ns
1275ns
3.56
4
9
100ns
225ns
575ns
1725ns
700ns
1225ns
1075ns
2400ns
300ns
100ns
1775ns
3675ns
2.52
⎯
50
Double Precision Integer Add/Sub
Integer Multiply
4
23
69
28
51
43
96
12
4
575
760
55
Double Precision Integer Add/Sub
Floating Add/Sub
9
18
34
9
Extended Floating Add/Sub
Floating Multiply
50
477
564
50
Extended Floating Point Multiply
Branch (Taken)
17
8
Branch (Not Taken)
4
⎯
263
Flt'g' Point Polynomial Step (Mul+Add/Sub)
Ext Flt'g' Point Polynomial Step (Mul/Sub)
DAIS Mix (MIPS)
27
51
⎯
71
147
⎯
2400
41/59
PACE1757ME BUILT-IN FUNCTIONS
A core set of additional instructions have been included in the PACE1757ME. These instructions use the Built-In Function (BIF)
opcode space. The objective of these new opcodes is to enhance the performance of the PACE in critical application areas
such as navigation, DSP, transcendentals and other LINPAK and matrix type instructions. Below is a list of the BIFs and their
execution times (N = the number of elements in the vector being processed).
Address
Mode
Number of
Clocks
Instruction
Mnemonic
Notes
Memory Parametric Dot Product - Single
Memory Parametric Dot Product - Double
3 x 3 Register Dot Product
VDPS
VDPD
R3DP
MACD
4F06
4F3(RA)
4F1(RA)
4F03
4F02
7 • N -2
4
10 + 8 • N
Interruptable
10 + 16 • N Interruptable
6
8
Double Precision Multiply Accumulate
Polynomial POLY
Clear Accumulator CLAC
Store Accumulator (32-Bit)
4F00
STA
4F08
4F04
4F05
4F07
4F0F
4F0D
4F0E
7
11
9
Store Accumulator (48-Bit)
STAL
LAC
Load Accumulator (32-Bit)
Load Accumulator Long (48-Bit)
Move MMU Page Block
LACL
MMPG
LTAR
LTBR
9
16 + 8 • N
Priveleged
Load Timer A Reset Register
Load Timer B Reset Register
4
4
Do c um e nt # MICRO-10 REV B
Pa g e 6 o f 34
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