November 2006
rev 0.2
ASM2P5T9070A
Pin Configuration
Top View – TSSOP Package
48
1
GND
VDD
GL
VDD
47
46
2
3
4
VDD
GND
GND
VDD
GND
GND
GND
45
44
5
6
43
G1
VDD
7
8
42
41
40
VDD
Q3
Q4
Q2
Q1
9
GND
VDD
ASM2P5T9070A
39
GND
VDD
10
11
12
13
38
37
Q5
Q6
GND
A
36
VDD
35
34
33
VDD
GND
Q10
Q9
VDD
14
15
16
GND
Q7
Q8
32
17
18
VDD
VDD
31
30
19
20
G2
GND
GND
VDD
29
28
GND
21
22
23
GND
VDD
27
26
25
VDD
GND
NC
24
NC
Pin Description
Symbol I/O
Type
LVTTL
Description
Clock input
A
I
G1
I
LVTTL
Gate for outputs Q1 through Q5. When G1 is LOW, these outputs are enabled. When G1
is HIGH, these outputs are asynchronously disabled to the level designated by GL1.
G2
GL
I
LVTTL
LVTTL
Gate for outputs Q6through Q10. When G2 is LOW, these outputs are enabled. When G2
is HIGH, these outputs are asynchronously disabled to the level designated by GL1.
Specifies output disable level. If HIGH, the outputs disable HIGH. If LOW, the outputs
disable LOW.
I
Qn
VDD
GND
O
LVTTL
PWR
PWR
Clock outputs
Power supply for the device core, inputs, and outputs
Power supply return for power
NOTE: Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control signals to minimize the
possibility of runt pulses or be able to tolerate them in down stream circuitry.
2.5V Single Data Rate 1:10 Clock Buffer Terabuffer
2 of 9
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
