November 2006
ASM2P2310A
rev 0.3
Pin Configuration
CLK
VDD
1
2
3
24
23
22
GND
VDD
VDD
1Y0
4
5
6
21
20
19
2Y0
1Y1
1Y2
GND
2Y1
GND
7
18
GND
2Y2
GND
1Y3
1Y4
VDD
8
9
17
16
2Y3
VDD
10
15
VDD
2G
11
12
14
13
1G
2Y4
Pin Description
Pin #
1
2
3
4
5
6
7
Pin Name
GND
VDD
Type
P
P
O
O
O
P
P
O
Description
Ground Pin
DC Power supply, 2.3 V – 3.6V
Buffered Output Clock
Buffered Output Clock
Buffered Output Clock
Ground Pin
1Y0
1Y1
1Y2
GND
GND
1Y3
1Y4
VDD
Ground Pin
8
9
10
Buffered Output Clock
Buffered Output Clock
DC power supply, 2.3V – 3.6V
O
P
Output enable control for 1Y[0:4] outputs. This output enable is active-high,
meaning the 1Y[0:4] clock outputs follow the input clock (CLK) if this pin is logic
high.
11
12
13
1G
2Y4
2G
I
O
I
Buffered Output Clock
Output enable control for 2Y[0:4] outputs. This output enable is active-high,
meaning the 2Y[0:4] clock outputs follow the input clock (CLK) if this pin is logic
high.
14
15
16
17
18
19
20
21
22
23
24
VDD
VDD
P
P
O
O
P
P
O
O
P
P
I
DC power supply, 2.3V – 3.6V
DC power supply, 2.3V – 3.6V
Buffered Output Clock
Buffered Output Clock
Ground Pin
2Y3
2Y2
GND
GND
2Y1
2Y0
VDD
Ground Pin
Buffered Output Clock
Buffered Output Clock
DC power supply, 2.3V – 3.6V
DC power supply, 2.3V – 3.6V
Input reference frequency
VDD
CLK
2.5-V TO 3.3-V High-Performance Clock Buffer
2 of 11
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
