July 2005
rev 0.4
ASM2I99446
ASM2I99446
Z0=50Ω
Z0=50Ω
Pulse
Generator
Z=50Ω
RT=50Ω
Figure 4. CCLK0, 1 ASM2I99446 AC test reference for VCC = 3.3V and VCC = 2.5V
VCC
CCLK
VCC ÷2
GND
VCC = 3.3V VCC = 2.5V
2.4
1.8V
0.6V
VCC
QX
V
CC ÷2
0.55
GND
t(LH)
t(HL)
tR
tF
Figure 5. Output Transition Time Test Reference
Figure 6. Propagation Delay (tPD
) Test Reference
VCC
VCC ÷2
GND
CCLK
VCC
VCC ÷2
GND
VCC
QX
V
CC ÷2
VOH
VCC ÷2
GND
t(LH)
t(HL)
SK(P) │tPLH- tPHL
GND
tSK(LH)
tSK(HL)
t
│
The pin-to-pin skew is defined as the worst case
difference in propagation delay between any similar
delay path within a single device
Figure 8. Propagation Delay (tSK(P)
) Test Reference
Figure 7. Output–to–Output Skew tSK(LH,HL)
VCC
VCC ÷2
GND
TJIT(CC) = |TN -TN + 1|
TN
TN + 1
tP
The variation in cycle time of a signal between adjacent
cycles, over a random sample of adjacent cycle pairs
T0
Figure 10. Cycle–to–Cycle Jitter
DC (tP ÷T0 Χ 100%)
The time from the PLL controlled edge to the
non-controlled edge, divided by the time
between PLL controlled edges, expressed as a
percentage.
Figure 9. Output Duty Cycle (DC) Reference
2.5V and 3.3V LVCMOS Clock Distribution Buffer
8 of 14
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
