November 2006
rev 1.6
ASM1232LP/LPS
Detailed Description
tR
The ASM1232LP/LPS monitors the microprocessor or
microcontroller power supply and generates reset signal,
both active HIGH and Active LOW, that halt processor
operation whenever the power supply voltage levels are
outside a predetermined tolerance.
V
VCCTP
CCTP(MAX)
VCCTP(MIN)
tRPU
VCC
RESET
RESET
RESET and RESET outputs
RESET is an active HIGH signal developed by a CMOS
push-pull output stage and is the logical opposite to RESET.
VOH
VOL
RESET is an active LOW signal. It is developed with an open
drain driver. A pull up resistor of typical value 10kΩ to 50kΩ is
required to connect with the output.
Figure 1: Timing Diagram : Power Up
Trip Point Tolerance Selection
The TOL input is used to determine the level VCC can vary
tF
VCC
below 5V without asserting a reset. With TOL conected to
VCC, RESET and RESET become active whenever VCC falls
V
(MAX)
CCTP
V
CCTP
below 4.5V. RESET and RESET become active when the
VCC falls below 4.75V if TOL is connected to ground.
V
(MIN)
CCTP
After VCC has risen above the trip point set by TOL, RESET
RESET
RESET
tRPD
and RESET remain active for a minimum time period of
250ms. On power-down, once VCC falls below the reset
VOH
VOL
threshold RESET stays LOW and is guaranteed to be 0.4V or
less until VCC drops below 1.2V. The active HIGH reset signal
Figure 2: Timing Diagram : Power Down
is valid down to a VCC level of 1.2V also.
TRIP Point Voltage
Tolerance
Select
(V)
Tolerance
Min
Nom
Max
Application Information
TOL = VCC
TOL = GND
Manual Reset Operation
10%
5%
4.25 4.37
4.5 4.62
4.49
4.74
Push-button switch input, PBRST, allows the user to override
the internal trip point detection circuits and issue reset
signals. The pushbutton input is debounced and is pulled
HIGH through an internal 40kΩ resistor.
3 of 10
5V µP Power Supply Monitor and Reset Circuit
Notice: The information in this document is subject to change without notice
PULSECORE [ PulseCore Semiconductor ]
