November 2006
rev 1.6
ASM1232LP/LPS
Pin Configuration
DIP/SO/MicroSO
SO
1
8
VCC
16 NC
NC
PBRST
1
7
6
5
2
3
VCC
15
ST
ASM1232LP
ASM1232LPS-2
ASM1232LPU
TD
2
3
PBRST
NC
TOL
NC
14
RESET
RESET
4
GND
13 ST
4
TD
NC
ASM1232LPS
NC
5
6
12
11
10
9
RESET
NC
TOL
NC
7
8
RESET
GND
Pin Description
Pin #
8-Pin Package
Pin #
16-Pin Package
Pin
Name
Function
1
2
2
PBRST
TD
Debounced manual pushbutton RESET input.
Watchdog time delay selection. (tTD = 150ms for TD = GND, tTD = 610ms
for TD=Open, and tTD = 1200ms for TD = VCC).
4
Selects 5% (TOL connected to GND) or 10% (TOL connected to VCC
trip point tolerance.
)
3
4
6
8
TOL
GND
Ground.
Active HIGH reset output. RESET is active:
1. If VCC falls below the reset voltage trip point.
2. If PBRST is LOW.
5
9
RESET
3. If ST is not strobed LOW before the timeout period set by TD expires.
4. During power-up.
6
7
8
11
13
15
RESET
ST
Active LOW reset output. (See RESET).
Strobe input.
VCC
5V power.
1,3,5,7,
10,12,14,16
-
NC
No internal connection.
2 of 10
5V µP Power Supply Monitor and Reset Circuit
Notice: The information in this document is subject to change without notice
PULSECORE [ PulseCore Semiconductor ]
