LYT2002-2005
Figure 6. PCB Layout Example using eSIP Package.
Figure 5. PCB Layout Example using SO-8C Package.
Drain Clamp Optimization
Quick Design Checklist
LYTSwitch-2 ICs use primary-side sensing to regulate the output.
The voltage that appears on the primary winding is a reflection of the
secondary winding voltage while the internal is off. Leakage inductance
induced ringing can affect output regulation. Optimizing the drain
clamp to minimize high frequency ringing will give the best regulation.
Figure 7 shows the desired drain voltage waveform; while Figure 8
shows a large undershoot due to a leakage inductance induced ring.
Ringing can be reduced (and hence regulation improved) by adjusting
the value of the resistor in series with the primary clamp diode.
As with any power supply design, all LYTSwitch-2 family designs should
be verified on the bench to make sure that component specifications
are not exceeded under worst-case conditions. The following set of
tests is strongly recommended:
1. Maximum drain voltage – Verify that the peak VDS does not
exceed 680 V at the highest input voltage and maximum output
power.
2. Drain current – At maximum ambient temperature, maximum and
minimum input voltage and maximum output load, review drain
current waveforms at start-up for any signs of transformer
saturation or excessive leading edge current spikes. LYTSwitch-2
devices have a leading edge blanking time to prevent premature
termination of the ON-cycle, but limit leading edge spikes to less
than the maximum time as specified in the data sheet.
3. Thermal check – At maximum output power, for both minimum
and maximum input voltage and maximum ambient temperature;
verify that temperature limits are not exceeded for LYTSwitch-2,
transformer, output diodes and output capacitors. Thermal
margin should be provided to allow for part-to-part variation in the
RDS(ON) of the LYTSwitch-2 device. For optimum regulation, a
SOURCE pin temperature of 90 ºC is recommended.
Addition of a Bias Circuit for Higher Light Load Efficiency and
Lower No-load Input Power Consumption
The addition of a bias circuit can decrease the no-load input power
from ~200 mW to less than 30 mW at 230 VAC input.
The power supply schematic shown in Figure 4 has the bias circuit
incorporated. Diode D2, C5 and R9 form the bias circuit.
Diode D2 rectifies the output and C5 is the filter capacitor. A 1 mF
capacitor is recommended to maintain the minimum bias voltage at
low switching frequencies.
The recommended current into the BYPASS pin is equal to IC supply
current (~0.5 mA) at the minimum bias winding voltage. The BYPASS
pin current should not exceed 3 mA at the maximum bias winding
voltage. The value of R9 is calculated according to (VBIAS-VBP)/IS2,
where VBIAS (10 V typical) is the voltage across C5, IS2 (0.5 mA typ.) is
the IC supply current and VBP (6.2 V typ.) is the BYPASS pin voltage.
Design Tools
Up-to-date information on design tools can be found at the Power
Integrations web site: www.power.com
The parameters IS2 and VBP are provided in the parameter table of the
LYTSwitch-2 data sheet. Diode D2 can be a low-cost type such as
FR102, 1N4148 or BAV19/20/21.
6
Rev. B 09/15
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