LNK623-626
Drain Clamp
Recommended Clamp Circuits
RC2
DC2
RC2
CC1
CC1
RC1
DC1
RC1
DC1
PI-5107-110308
PI-5108-110308
Figure 9. RCD Clamp, Low Power or Low Leakage Inductance Designs.
RCD Clamp With Zener Bleed. High Power or High Leakage Inductance Designs.
Components R±, R2, C3, VR± and D1 in figure 4 comprise the
clamp. This circuit is preferred when the primary leakage
inductance is greater than ±21 μH to reduce drain voltage
overshoot or ringing present on the feedback winding. For best
output regulation, the feedback voltage must settle to within ±5
at 2.± μs from the turn off of the primary MOSFET. This requires
careful selection of the clamp circuit components. The voltage of
VR± is selected to be ~205 above the reflected output voltage
(VOR). This is to clip any turn off spike on the drain but avoid
conduction during the flyback voltage interval when the output
diode is conducting. The value of R± should be the largest value
that results in acceptable settling of the feedback pin voltage and
peak drain voltage. Making R± too large will increase the
discharge time of C3 and degrade regulation. Resistor R2
dampens the leakage inductance ring. The value must be large
enough to dampen the ring in the required time but must not be
too large to cause the drain voltage to exceed 680 V.
RC2
CC1
RC1
DC1
PI-5107-110308
If the primary leakage inductance is less than ±21 μH, VR± can
be eliminated and the value of R± increased. A value of 470 kΩ
with an 820 pF capacitor is a recommended starting point.
Verify that the peak drain voltage is less than 680 V under all
line and load conditions. Verify the feedback winding settles to
an acceptable limit for good line and load regulation.
Effect of Fast (500 ns) versus Slow (2 μs) Recovery
Diodes in Clamp Circuit on Pulse Grouping and Output
Ripple.
A slow reverse recovery diode reduces the feedback voltage
ringing. The amplitude of ringing with a fast diode represents
85 error in Figure ±0.
Black Trace: DC± is a FR±07 (fast type, trr = 100 ns)
Gray Trace: DC± is a ±N4007G (standard recovery, trr = 2 us)
Figure 10. Effect of Clamp Diode on Feedback Pin Settling. Clamp Circuit (top).
Feedback Pin Voltage (bottom).
8
Rev. E 09/09
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