LNK574
CB
DB
RS
CS
DBP
RBP
RFB2
CFB
DO
CO
CBP
R6
Transformer
RFB1
U1
J3
–
+
T1
HV DC
IN
LV DC
OUT
–
+
PI-6098-092410
Figure 5. PCB Layout of a 2.1 W, 6 V, 350 mA Charger.
The following minimum set of tests is strongly recommended:
1. Maximum drain voltage – Verify that VDS does not exceed
660 V at the highest input voltage and peak (overload) output
power. This margin to the 700 V BVDSS specification gives
margin for design variation, especially in clampless designs.
2. Maximum drain current – At maximum ambient temperature,
maximum input voltage and peak output (overload) power,
verify drain current waveforms for any signs of transformer
saturation and excessive leading-edge current spikes at
startup. Repeat under steady state conditions and verify that
the leading-edge current spike event is below ILIMIT(MIN) at the
end of the tLEB(MIN). Under all conditions, the maximum drain
current should be below the specified absolute maximum
ratings.
3. Thermal check – At specified maximum output power,
minimum input voltage and maximum ambient temperature,
verify that the temperature specifications are not exceeded
for LinkZero-LP, transformer, output diode and output
capacitors. Enough thermal margin should be allowed for
part-to-part variation of the RDS(ON) of LinkZero-LP as speci-
fied in the data sheet. Under low line and maximum power,
maximum LinkZero-LP source pin temperature of 100 °C is
recommended to allow for these variations.
Thermal Considerations
The copper area underneath the LinkZero-LP (U1) acts not only
as a single point ground, but also as a heatsink. As it is
connected to the quiet source node, this area should be
maximized for good heat sinking of U1. The same applies to
the cathode of the output diode.
Y Capacitor
The placement of the Y-type capacitor (if used) should be
directly from the primary input filter capacitor positive terminal to
the common/return terminal of the transformer secondary.
Such a placement will route high magnitude common-mode
surge currents away from U1. Note: If an input π EMI filter is
used, the inductor in the π filter should be placed between the
negative terminals on the input filter capacitors.
Output Diode (DO)
For best performance, the area of the loop connecting the
secondary winding, the output diode (DO) and the output filter
capacitor (CO)should be minimized. In addition, sufficient
copper area should be provided at the anode and cathode
terminals of the diode for heat sinking. A larger area is preferred
at the electrically “quiet” cathode terminal. A large anode area
can increase high frequency conducted and radiated EMI.
Resistor RS and CS represent the secondary side RC snubber.
4. Negative drain voltages – clampless designs may allow the
drain voltage to ring below source and cause reverse
currents to flow from source to drain. Verify that any such
current remains within the envelope shown in Figure 9.
Quick Design Checklist
As with any power supply design, all LinkZero-LP designs
should be verified on the bench to make sure that component
specifications are not exceeded under worst-case conditions.
6
Rev. B 12/07/10
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