LNK574
consumption is determined by the BYPASS pin capacitor C3.
No-load power consumption can be reduced by a capacitor
with higher value. Higher C3 capacitor values will tend to
increase the output ripple in PD mode - See LinkZero-LP
Design Considerations section below.
When the LinkZero-LP is in PD mode, the time taken for the
BYPASS pin voltage to discharge to VBPPDRESET (~3 V) determines
the duration of the PD off-time. The duration of the PD off time
also determines the ripple on the output voltage.
A clampless primary circuit is achieved due to the very tight
tolerance current limit trimming techniques used in manufacturing
the LinkZero-LP, plus the transformer construction techniques
used. The peak drain voltage is therefore limited to typically
less than ꢀꢀ0 V at 26ꢀ VAC, providing significant margin to the
700 V minimum drain voltage specification (BVDSS).
If components Dꢀ and R2 are not used in Figure 4, this time is
determined purely by the choice of C3. If however Dꢀ and R2
are used to provide an external BYPASS pin supply, then a
combination of the energy stored in Cꢀ and C3 determine the
PD off time before the BYPASS pin voltage reaches the VBP(PU)
(~3 V).
Output rectification and filtering is achieved with output rectifier
D7 and filter capacitor C7. Due to the auto-restart feature, the
average short circuit output current is significantly less than 1 A,
allowing low current rating and low cost rectifier D7 to be used.
Output circuitry is designed to handle a continuous short circuit
on the power supply output. Although not necessary in this
design, a preload resistor may be used at the output of the
supply to reduce output voltage at no-load.
In either case, Cꢀ is completely discharged through R3 and R4
during the PD off time (Dꢀ prevents the BYPASS capacitor C3
being discharged through this path). Cꢀ is therefore kept as
small as possible to reduce the power supply no-load input
power consumption associated with recharging this capacitor
at the start of the next PD on time. The minimum value of Cꢀ is
determined by the time constant set up with the feedback
resistors R3 and R4 to avoid excessive cycle by cycle ripple on
Cꢀ influencing the output voltage regulation. The typical choice
for Cꢀ is between 100 nF and 330 nF.
LinkZero-LP Power Down (PD) Mode Design
Considerations
When Dꢀ and R2 are used, the minimum value of bias winding
capacitor Cꢀ is again governed by voltage regulation performance
so the value of BYPASS pin capacitor C3 is typically reduced to
reduce PD off time period if required. A minimum C3 value of
47 nF is recommended.
The LinkZero-LP goes into PD mode when the output power
supply load is reduced enough that 160 consecutive switching
cycles are skipped twice with only one active switching cycle in
between the two sets of 160 skipped switching cycles. This
corresponds to ~0.65 of the full load power capability of the
LinkZero-LP.
PCB Layout Considerations
Even when the power supply output load is completely removed,
any preload resistor on the output and the components
LinkZero-LP Layout Considerations
Layout
connected to the bias winding still represent a load on the
transformer. The feedback circuitry connected to the bias winding
should therefore be designed to represent <0.65 of the power
supply full load. Otherwise LinkZero-LP will not be able to
detect a no-load condition on the output and will not enter PD
mode thereby disabling the benefit of zero no-load input power.
See Figure ꢀ for a recommended circuit board layout for
LinkZero-LP (U1).
Single Point Grounding
Use a single point ground (Kelvin) connection from the input
filter capacitor to the area of copper connected to the SOURCE
pins.
In the case of the design of Figure 4, the power supply full load
output power is 2.1 W (6 V, 3ꢀ0 mA). The bias winding load
should therefore be designed to be <<0.65 of this (<12.6 mW). In
the example of Figure 4, the average no-load voltage across
bias winding capacitor Cꢀ is approximately 20 V. The loading of
R3, R4 and R2 (if used) should therefore be chosen to present
<12.6 mW load with this bias voltage. In the case shown, the R2
path consumes ~3.3 mW and R3 and R4 also consumes ~3.3 mW.
So the total consumption of 6.6 mW meets the criteria necessary
to ensure the power supply will enter PD mode when the power
supply load is removed. Adjusting the power consumption of
the circuitry connected to the bias winding can therefore be
used to adjust the power supply output power threshold at
which the LinkZero-LP goes into PD mode.
Bypass Capacitor (CBP), FEEDBACK Pin Noise Filter
Capacitor (CFB) and Feedback Resistors
To minimize loop area, these two capacitors should be physically
located as near as possible to the BYPASS and SOURCE pins,
and FEEDBACK pin and SOURCE pins respectively. Also note
that to minimize noise pickup, feedback resistors RFB1 and RFB2
are placed close to the FEEDBACK pin.
Primary Loop Area
The area of the primary loop that connects the input filter
capacitor, transformer primary and LinkZero-LP should be kept
as small as possible.
Primary Clamp Circuit
It can be seen therefore that, if desired, PD mode can be
avoided altogether simply by adding a preload resistor on the
output of the power supply or increasing the load on the bias
winding to >0.65 (plus margin) of the power supply maximum
power capability.
An external clamp may be used to limit peak voltage on the
DRAIN pin at turn off. This can be achieved by using an RCD
clamp or a Zener (~200 V) and diode clamp across the primary
winding. In all cases, to minimize EMI, care should be taken to
minimize the circuit path from the clamp components to the
transformer and LinkZero-LP (U1).
5
www.powerint.com
Rev. B 12/07/10
POWERINT [ Power Integrations ]
