INT100
Pin Functional Description
Pin 1:
Pin 7:
Pin 12,13,14:
VDD supplies power to the logic, high-
side interface, and low-side driver.
LSRTNisthepowerreferencepointfor
the low-side circuitry, and should be
connected to the source of the low-side
MOSFET and to the COM pin.
HS RTN is the power reference point
forthehigh-sidecircuitry,andshouldbe
connected to the source of the high-side
MOSFET.
Pin 2:
Active-low logic level input HS IN
controls the high-side driver output.
Pin 8:
Pin 15:
LS OUT is the driver output which
controls the low-side MOSFET.
VDDH supplies power to the high-side
control logic and output driver. This is
normally connected to a high-side
referenced bootstrap circuit or can be
supplied from a separate floating power
supply.
Pin 3:
Active-high logic level input LS IN
controls the low-side driver output.
Pin 11:
HS OUT is the driver output which
controls the high-side MOSFET.
Pin 4, 5:
COM connection is used as the analog
reference point for the circuit.
INT100 Functional Description
5 V Regulators
This guarantees that the high-side
MOSFET will be off during power-up
or fault conditions.
signals. These signals are used by the
discriminator to reject spurious noise.
The combination of differential
communication with the precise timing
provides maximum immunity to noise.
Both low-side and high-side driver
circuitsincorporatea5Vlinearregulator
circuit. The low-side regulator provides
the supply voltage for the control logic
andhigh-voltagelevelshiftcircuit. This
allows HS IN and LS IN to be directly
compatible with 5 V CMOS logic
without the need of an external 5 V
supply. Thehigh-side regulatorprovides
thesupplyvoltageforthenoiserejection
circuitry and high-side control logic.
Level Shift
The level shift control circuitry of the
low-sidedriverisconnectedtointegrated
high-voltage N-channel MOSFET
transistors which perform the level-
shifting function for communication to
the high-side driver. Controlled current
capability allows the drain voltage to
float with the high-side driver. Two
individual channels produce a true
differential communication channel for
accurately controlling the high-side
driver in the presence of fast moving
high-voltage waveforms. The high
voltage level shift transistors employed
exhibit very low output capacitance,
minimizing the displacement currents
between the low-side and high-side
drivers during fast moving voltage
transients created during switching of
the external MOSFETs. As a result,
powerdissipationisminimizedandnoise
immunity optimized.
Simultaneous Conduction Lockout
A latch prevents the low-side driver and
high-side driver from being on at the
sametime,regardlessoftheinputsignals.
Delay Circuit
The delay circuit matches the low-side
propagation delay with the combination
of the pulse circuit, high voltage level
shift, and high-side driver propagation
delays. This ensures that the low-side
driver and high-side driver will never be
on at the same time during switching
transitions in either direction.
Undervoltage Lockout
The undervoltage lockout circuit for the
low-side driver disables both the LS
OUT and HS OUT pins whenever the
VDD power supply falls below typically
9.0 V, and maintains this condition until
the VDD power supply rises above
typically 9.35 V. This guarantees that
both MOSFETs will remain off during
power-up or fault conditions.
Driver
The CMOS drive circuitry on both low-
side and high-side driver ICs provide
drive power to the gates of the external
MOSFETs. The drivers consist of a
CMOSbuffercapableofdrivingexternal
transistor gates at up to 15 V.
The undervoltage lockout circuit for the
high-side driver disables the HS OUT
pin whenever the VDDH power supply
fallsbelowtypically9.0V,andmaintains
this condition until the VDDH power
supply rises above typically 9.35 V.
The pulse circuit provides the two high-
voltagelevelshifterswithprecisetiming
C
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POWERINT [ Power Integrations ]
