InnoSwitch-CH
Applications Example
ꢁꢄC
ꢋꢀ ꢕꢕꢀ ꢃꢖꢗ ꢃꢌꢀ
ꢊꢃ.ꢄ ꢊꢃ.ꢄ
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10ꢚ ꢋꢦꢢꢧ
ꢤꢬꢭꢥ
ꢕꢞꢞꢟꢠꢟeꢆꢠꢡ
ꢢꢝ ꢀꢅꢣ ꢤꢚꢥ
ꢊꢄ.ꢍ ꢊꢃ.ꢄ ꢊꢈ.1 ꢊꢃ.ꢊ
7ꢊ.ꢐ 7ꢊ.ꢘ 7ꢊ.ꢍ 7ꢊ.7
ꢅꢊ
100 ꢎꢇ
ꢃ00 ꢉꢏꢅ
ꢖꢦꢂꢋꢦꢢꢧ ꢁꢆꢎꢨꢝ
7
7
ꢊ
ꢘ
ꢋꢄ
ꢃ.7 µꢌ
ꢀ ꢁꢂ ꢃ ꢄ
ꢃ
ꢐ
ꢍ
Rꢊ
100 ꢗΩ
1ꢚ
ꢅ1
1 ꢆꢇ
ꢄꢈ0 ꢉ
ꢅ10
ꢈꢍ0 µꢇ
ꢍ.ꢐ ꢉ
ꢅꢘ
R7 1.ꢈ ꢆꢇ
ꢄ0 Ω ꢄ00 ꢉ
R1
ꢄ00 ꢗΩ
Rꢘ
ꢐꢃ ꢗΩ
1ꢚ
R10
ꢐꢐ0 ꢗΩ
ꢑ1
R1ꢃ ꢑꢇꢋR1ꢍ00ꢂ7
ꢐ0 Ω
ꢍ00 ꢉ
ꢑꢐ
Rꢒꢄꢓꢏꢂ1ꢐꢂꢇ
ꢈ
1
ꢄ
ꢇ1
ꢐ.1ꢈ ꢏ
ꢈꢉꢊꢈ-
ꢔ1
ꢅ1ꢍ
1 µꢇ
ꢈ0 ꢉ
ꢅꢄ
ꢅꢃ
ꢕꢕ1ꢍꢄ1
ꢋꢀ - ꢃꢌꢍ
ꢁꢄC
ꢖꢅ
ꢊ.ꢄ µꢇ
ꢊ.ꢄ µꢇ
ꢃ00 ꢉ
ꢃ00 ꢉ
Rꢔ1
10 Ω
ꢅ7
ꢄ.ꢄ µꢇ
Rꢈ
ꢃ7 Ω
ꢅꢈ
ꢄꢄ µꢇ
1ꢍ ꢉ
ꢄꢈ ꢉ
Rꢃ
ꢐ ꢗΩ
ꢐ
R11
100 ꢗΩ
ꢝ
InnoSwitch-CH
ꢛ1
ꢁꢖꢖꢄ0ꢄꢐꢜ
ꢈ
S
ꢑꢃ
Rꢒꢄꢓꢏꢂ1ꢐꢂꢇ
Cꢐꢇꢆꢅꢐꢔ
ꢑꢓ
ꢅ1ꢈ
100 ꢎꢇ
100 ꢉ
ꢓꢏꢏ
IS
ꢅꢍ
1 µꢇ
ꢄꢈ ꢉ
ꢋ1
100 µꢌ
ꢅꢆꢇ
ꢀꢁꢂ7ꢃꢄꢃꢂ11101ꢃ
Figure 14. 5 V, 2 A Universal Input Charger.
effectively limits the turn-off voltage spike at the DRAIN pin of U1 to
a safe value.
The circuit shown in Figure 14 is a low cost, very high efficiency
charger designed to provide 5 V, 2 A CV/CC charging, using an
INN2023K integrated power supply controller.
The InnoSwitch-CH IC is self-starting, using an internal high-voltage
current source to charge the PRIMARY BYPASS pin capacitor (C6)
when AC is first applied. During normal operation the primary-side
controller is powered from an auxiliary winding on the transformer
T1. Output of the auxiliary (or bias) winding is rectified using diode
D2 and filtered using capacitor C5. Resistor R4 limits the current
being supplied to the PRIMARY BYPASS pin of the InnoSwitch-CH IC
(U1) to be close to the IC supply current so as to minimize no-load
input power.
This single 5 V output charger design features DoE Level 6 and EC
CoC 5 compliance (84% measured vs. 79% requirement) and <10 mW
no-load input power. The integration offered by InnoSwitch-CH
devices reduces the total component count from typically >45 to only
32. The built-in secondary-side synchronous rectification (SR)
controller of U1, allows expensive high current Schottky barrier diodes
to be replaced with lower cost MOSFETs while increasing efficiency
and removing hot spots. With control on the secondary-side, cross
conduction problems normally associated with SR are eliminated
under all conditions.
Output regulation is achieved using ON/OFF control, the number of
enabled switching cycles are adjusted based on the output load. At
high-load, most switching cycles are enabled, and at light-load or
no-load, most cycled are disabled or skipped. Once a cycle is enabled,
the MOSFET will remain on until the primary current ramps to the
device current limit for the specific operating state. There are four
operating states (current limits) arranged such that the frequency
content of the primary current switching pattern remains out of the
audible range until at light-load where the transformer flux density
and therefore audible noise generation is at a very low level.
The input stage required a small thermistor (RT1) to prevent inrush
currents exceeding the specification of D3-D6 and causing fuse F1
to open.
The total input capacitance of capacitor C2 and C4 is sufficient to
maintain full output power delivery at 85 VAC, the converter being
able to operate at the minimum DC voltage, just before the next AC
cycle refreshes the input. The DC voltage is applied to the primary
winding of T1. The other end of the primary winding is driven by the
MOSFET inside the InnoSwitch-CH IC.
The secondary-side of the InnoSwitch-CH IC provides output voltage,
output current sensing and drive to a MOSFET providing synchronous
rectification.
A low-cost RCD clamp formed by diode D1, resistors R1 and R14, and
capacitor C1 limits the peak drain voltage of the InnoSwitch-CH IC at
the instant of turn-off of the MOSFET. The clamp helps dissipate the
energy stored in the leakage reactance of transformer T1 and
The secondary of the transformer is rectified by MOSFET Q1 and
filtered by capacitor C10. Resistor R7 and C9 limit high-frequency
8
Rev. J 10/17
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