OXFORD SEMICONDUCTOR LTD.
OXmPCI952
P
ERFORMANCE
C
OMPARISON
Feature
Internal serial channels
Integral IEEE 1284 EPP/ECP parallel port
Multi-function PCI device
Support for PCI Power Management
Zero wait-state write operation
No. of available Local Bus interrupt pins
DWORD access to UART Interrupt Source
Registers & FIFO Levels
Good-Data status
Full Plug and Play with external EEPROM
External 1x baud rate clock
Max baud rate in normal mode
Max baud rate in 1x clock mode
FIFO depth
Sleep mode
Auto Xon/Xoff flow
Auto CTS#/RTS# flow
Auto DSR#/DTR# flow
No. of Rx interrupt thresholds
No. of Tx interrupt thresholds
No. of flow control thresholds
Transmitter empty interrupt
Readable status of flow control
Readable FIFO levels
Clock prescaler options
Rx/Tx disable
Software reset
Device ID
9-bit data frames
RS485 buffer enable
Infra-red (IrDA)
OXmPCI952
2
yes
yes
yes
yes
1
11
yes
yes
yes
yes
15 Mbps
60 Mbps
128
yes
yes
yes
yes
128
128
128
yes
yes
yes
248
yes
yes
yes
yes
yes
yes
16C552 +
PCI Bridge
0
no
no
no
no
2
no
no
yes
no
115 Kbps
n/a
16
no
no
no
no
4
1
n/a
no
no
no
n/a
no
no
no
no
no
no
16C652 +
PCI Bridge
0
no
no
no
no
2
no
no
yes
no
1.5 Mbps
n/a
64
yes
yes
yes
no
4
4
4
no
no
no
2
no
no
no
no
no
yes
Table 1: OXmPCI952 performance compared with PCI Bridge + generic UART combinations
Note 1:
Zero wait-state applies only to the internal UARTs (after the assertion of DEVSEL#).
Read operation incurs 1 wait state.
DS-0020 Jun 05
Page 6
OXFORD [ OXFORD SEMICONDUCTOR ]
